HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 3

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter lists all main features of the product family HYB18H1G321AF–10/11/14 and the ordering information.
1.1
• 1.8 V
• 1.8 V
• Monolithic 1Gbit GDDR3 with an internally programmable
• Two CS: 4096 rows and 512 columns (128 burst start
• Differential clock inputs (CLK and CLK)
• CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
• Write latencies of 3, 4, 5, 6, 7
• Burst sequence with length of 4, 8
• 4n pre fetch
• Short RAS to CAS timing for Writes
•
1) HYB: designator for memory components
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Part Number
HYB18H1G321AF–10/11/14
organization of either two separate 512MBit memories
(2048 K x 32 I/O x 8 banks) with separate Chip Select, or
one 1Gb memory (4096 K x 32 I/O x 8 banks)
locations) per bank
– One CS: 8192 rows and 512 columns (128 burst start
t
RAS
18H: VDDQ = 1.8V
1G: 1 Gbit
32: x32 organization
A: Product Revision
F: Lead and Halogen-Free
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
locations) per bank
Lockout support
V
V
DDQ
DD
core voltage
1)
IO voltage
Overview
Features
Organization
×32
3
•
• Data mask for write commands
• Single ended READ strobe (RDQS) per byte. RDQS edge-
• Single ended WRITE strobe (WDQS) per byte. WDQS
• DLL aligns RDQS and DQ transitions with Clock
• Programmable IO interface including on chip termination
• Autoprecharge option with concurrent auto precharge
• 8k Refresh (32ms)
• Autorefresh and Self Refresh
• PG-TFBGA-136 package
• Calibrated output drive. Active termination support
• RoHS Compliant Product
t
aligned with READ data
center-aligned with WRITE data
(ODT)
support
WR
Clock (MHz)
1000 @CL12
700 @CL11
900 @CL11
programmable for Writes with Auto-Precharge
1)
HYB18H1G321AF–10/11/14
Package
PG-TFBGA-136
Ordering Information
Internet Data Sheet
1-Gbit GDDR3
TABLE 1