CY14B101LA CYPRESS [Cypress Semiconductor], CY14B101LA Datasheet - Page 15

• Manufacturer Part Number: CY14B101LA
• Description: 1 Mbit (128K x 8/64K x 16) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Hardware STORE Cycle
Switching Waveforms
Document #: 001-42879 Rev. *C
Notes
Parameters
t
t
t
DHSB
PHSB
SS
29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
30. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
[29, 30]
DQ (Data Out)
HSB (OUT)
Address
HSB (OUT)
Write latch not set
Write latch set
HSB (IN)
HSB (IN)
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
Soft Sequence Processing Time
V
CE
CC
RWI
RWI
Address #1
t
SA
t
DELAY
Description
Soft Sequence
t
t
PHSB
DELAY
t
Command
PHSB
Figure 15. Soft Sequence Processing
Figure 14. Hardware STORE Cycle
Address #6
t
DHSB
PRELIMINARY
t
CW
t
SS
t
STORE
t
DHSB
Address #1
Min
15
20 ns
Soft Sequence
100kOhm resistor,
HSB pin is driven high to V
SRAM is disabled as long as HSB (IN) is driven low.
Command
HSB driver is disabled
Max
100
20
[23]
[29, 30]
CY14B101LA, CY14B101NA
Address #6
Min
15
25 ns
t
CW
t
LZHSB
Max
100
t
25
HHHD
t
CC
SS
only by Internal
Min
15
45 ns
Page 15 of 24
Max
100
25
Unit
ns
ns
μs
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