NAND01G-B STMICROELECTRONICS [STMicroelectronics], NAND01G-B Datasheet - Page 31

• Manufacturer Part Number: NAND01G-B
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND01G-B, NAND02G-B
6.5
Figure 14. Cache Program Operation
1. Up to 64 pages can be programmed in one Cache Program operation.
2. t
I/O
RB
+ Last page data loading time).
CACHEPG
Program
Page
Code
80h
Address
Inputs
is the program time for the last page + the program time for the (last 1)
Cache Program
The Cache Program operation is used to improve the programming throughput by
programming data using the Cache Register. The Cache Program operation can only be
used within one block. The Cache Register allows new data to be input while the previous
data that was transferred to the Page Buffer is programmed into the memory array.
Each Cache Program operation consists of five steps (refer to
1.
2.
3.
4.
Once the program operation has started the Status Register can be read using the Read
Status Register command. During Cache Program operations SR5 can be read to find out
whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while
SR6 indicates whether the Cache Register is ready to accept new data. If any errors have
been detected on the previous page (
to ‘1', while if the error has been detected on Page N the Error Bit SR0 will be set to '1’.
When the next page (Page N) of data is input with the Cache Program command, t
affected by the pending internal programming. The data will only be transferred from the
Cache Register to the Page Buffer when the pending program cycle is finished and the Page
Buffer is available.
If the system monitors the progress of the operation using only the Ready/Busy signal, the
last page of data must be programmed with the Page Program confirm command (10h).
If the Cache Program confirm command (15h) is used instead, Status Register bit SR5 must
be polled to find out if the last programming is finished before starting any other operations.
First Page
First of all the program setup command is issued (one bus cycle to issue the program
setup command then four bus write cycles to input the address), the data is then input
(up to 2112 Bytes/ 1056 Words) and loaded into the Cache Register.
One bus cycle is required to issue the confirm command to start the P/E/R Controller.
The P/E/R Controller then transfers the data to the Page Buffer. During this the device
is busy for a time of t
Once the data is loaded into the Page Buffer the P/E/R Controller programs the data
into the memory array. As soon as the Cache Registers are empty (after t
Cache program command can be issued, while the internal programming is still
executing.
Inputs
(Cache Busy time)
Data
tBLBH5
Program
Cache
Code
15h
Busy
Program
Page
Code
80h
(can be repeated up to 63 times)
WHBH2
Address
Inputs
Second Page
.
Inputs
Data
Cache Program
Confirm Code
tBLBH5
Page N-1
15h
), the Cache Program Error Bit SR1 will be set
Busy
80h
th
page (Program command cycle time
Address
Inputs
Last Page
Figure
tCACHEPG
Inputs
Data
Confirm Code
14):
Program
Page
Device operations
10h
Busy
WHBH2
Read Status
70h
Register
WHBH2
) a new
ai08672
SR0
31/64
is