M28W640FCT STMICROELECTRONICS [STMicroelectronics], M28W640FCT Datasheet - Page 9

• Manufacturer Part Number: M28W640FCT
• Description: 64 Mbit (4Mb x16, Boot Block) 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
mode. When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V
Down is enabled and the protection status of the
block cannot be changed. When Write Protect is at
V
be locked or unlocked. (refer to
Protection Register and Lock
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
IH
, the Lock-Down is disabled and the block can
IL
Figure 2., Logic Diagram
and Reset is at V
IH
the device is in active
Register).
and
IH
Table 1., Signal
Table 7., Read
the memory is
IL
, the Lock-
IL
,
state. When Reset is at V
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
Enable or a change of the address is required to
ensure valid data outputs.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
supply to the I/O pins and enables all Outputs to
be powered independently from V
tied to V
V
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see
teristics, for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
If V
power supply pin. In this condition V
stable until the Program/Erase algorithm is com-
pleted (see
V
measurements.
Note: Each device in a system should have
V
pacitor close to the pin. See
surement Load
should be sufficient to carry the required V
program and erase currents.
DD
DDQ
PP
PP
SS
DD
PP
PP
, V
Program Supply Voltage. V
Ground. V
is seen as a control input. In this case a volt-
Supply Voltage. V
Supply Voltage. V
is kept in a low voltage range (0V to 3.6V)
is in the range 11.4V to 12.6V it acts as a
DDQ
DD
or can use a separate supply.
and V
Table 17.
M28W640FCT, M28W640FCB
PPLK
SS
Circuit. The PCB track widths
PP
is the reference for all voltage
decoupled with a 0.1µF ca-
gives an absolute protection
and
DD
IH
DDQ
Table
, the device is in normal
Table 15., DC Charac-
PP
provides the power
Figure 8., AC Mea-
provides the power
can be applied in
18.).
DD
PP
PP
. V
PP
is both a
> V
DDQ
DD
PP
must be
and the
PP1
is only
can be
9/55
en-
PP