M34E02-FDW1G STMICROELECTRONICS [STMicroelectronics], M34E02-FDW1G Datasheet - Page 6

• Manufacturer Part Number: M34E02-FDW1G
• Description: 2 Kbit serial presence detect (SPD) EEPROM for double data rate (DDR1 and DDR2) DRAM modules
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
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Description
The M34E02 and M34E02-F are 2 Kbit serial EEPROM memories able to lock permanently
the data in its first half (from location 00h to 7Fh). This facility has been designed specifically
for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD).
All the information concerning the DDR1 or DDR2 configuration of the DRAM module (such
as its access speed, size and organization) can be kept write-protected in the first half of the
memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resettable. In addition, the devices
allow the entire memory area to be write protected, using the WC input (for example by
tieing this input to V
These I
organized as 256 × 8 bits.
I
The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the
I
(0110) to define the protection. These codes are used together with the voltage level applied
on the three chip enable inputs (E2, E1, E0).
The devices behave as a slave device in the I
synchronized by the serial clock. Read and Write operations are initiated by a Start
condition, generated by the bus master. The Start condition is followed by a device select
code and RW bit (as described in the Device select code table), terminated by an
acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for WRITE, and after a NoAck for READ.
Figure 1.
2
2
C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
C bus definition to access the memory area and a second device type identifier code
2
C-compatible electrically erasable programmable memory (EEPROM) devices are
Logic diagram
CC
).
Doc ID 10367 Rev 10
2
C protocol, with all memory operations
M34E02, M34E02-F
th
bit