IS42LS16800A ICSI [Integrated Circuit Solution Inc], IS42LS16800A Datasheet - Page 2

• Manufacturer Part Number: IS42LS16800A
• Description: 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 2.5V V
and 1.8V V
containing 134,217 ,728 bits. Internally configured as a
quad-bank DRAM with a synchronous interface. Each
16,777,216-bit bank is organized as 4,096 rows by 256
columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
Only partials of the memory array can be selected for Self-
Refresh and the refresh period during Self-Refresh is
progammable in 4 steps which drastically reduces the self
refresh current, depending on the case temperature of the
components in the system application.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
FUNCTIONAL BLOCK DIAGRAM
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
2
CKE
RAS
CAS
A10
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DDQ
or 3.3V
GENERATOR
COMMAND
DECODER
11
CLOCK
&
ADDRESS
LATCH
ROW
DD
8
and 3.3V V
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
11
DDQ
memory systems
Integrated Silicon Solution, Inc. — www.issi.com —
11
CONTROLLER
COUNTER
REFRESH
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
SELF
DD
ROW
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst
access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
11
4096
16
16
4096
4096
4096
DATA OUT
BUFFER
BUFFER
8
DATA IN
(x 16)
256K
COLUMN DECODER
ADVANCED INFORMATION Rev. 00A
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
DQM
I/O 0-15
ISSI
Vcc/Vcc
GND/GNDQ
1-800-379-4774
Q
06/01/02
®