V62C2162048L-100B MOSEL [Mosel Vitelic, Corp], V62C2162048L-100B Datasheet - Page 11

• Manufacturer Part Number: V62C2162048L-100B
• Description: Ultra Low Power 128K x 16 CMOS SRAM
• Manufacturer: MOSEL [Mosel Vitelic, Corp]

REV. 1.3 OCT 2001 V62C2162048L(L)
Data Retention Characteristics
Data Retention Waveform
Notes (Write Cycle)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CC
L-version includes this feature.
This Parameter is samples and not 100% tested.
For test conditions, see AC Test Condition, Figure A.
This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
This parameter is guaranteed, but is not tested.
WE is High for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition LOW.
All read cycle timings are referenced from the last valid address to the first transtion address.
for Data Retention
V
CE
CC
Parameter
(2)
Vcc_typ
(L Version Only) (T
t
CDR
V
IH
(L Version Only)
Symbol
V
I
t
t
CCDR
CDR
R
DR
Data Retention Mode
V
11
DR
V
DR
> 2.0V
CE > V
V
V
A
Test Condition
IN
IN
= 0
(1)
> V
< 0.2V
0
C to +70
CC
CC
- 0.2V or
- 0.2V
V
t
R
IH
0
Vcc_typ
C / -40
0
C to +85
V62C2162048L(L)
Min
2.0
t
0
RC
-
0
C)
Max
1
-
-
-
Unit
ns
ns
V
A