V62C2161024L-100T MOSEL [Mosel Vitelic, Corp], V62C2161024L-100T Datasheet
V62C2161024L-100T
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V62C2161024L-100T Summary of contents
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... BHE BLE CE REV. 1.1 April 2001 V62C2161024L(L) Functional Description The V62C2161024L is a Low Power CMOS Static RAM organized as 65,536 words by 16 bits. Easy memory exp- at 55ns ansion is provided by an active LOW (CE ) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed ...
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... Key Don’t Care Low High Recommended Operating Conditions Parameter Supply Voltage Input Voltage * V min = -2.0V for pulse width less than For Industrial Temperature REV. 1.1 April 2001 V62C2161024L(L) Symbol Vt PT Tstg Tbias BLE BHE I/O1-I/O8 I/O9-I/O16 X X High-Z High Data Out ...
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... AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 55ns/70ns/85ns Load for 100ns REV. 1.1 April 2001 V62C2161024L( 2.2 to 2.7V, Gnd = 0V Test Conditions Sym Min Max Min Max Min Max Min Max I ...
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... Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End BLE, BHE Setup to Write End REV. 1.1 April 2001 V62C2161024L(L) = 2.2V to 2.7V, Gnd = 0V Sym -55 Min Max Min Max Min Max Min Max ...
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... Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with Address valid prior to coincident with CE transition Low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition, Figure A. REV. 1.1 April 2001 V62C2161024L( ...
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... Address CE BLE/BHE WE Data In Data Out Timing Waveform of Write Cycle 2 (CE Controlled) Address CE BLE/BHE WE Data In Data Out Timing Waveform of Write Cycle 3 (BLE/BHE Controlled) Address CE BLE/BHE WE Data In Data Out REV. 1.1 April 2001 V62C2161024L( ( (4) High-Z t OHZ ( ...
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... OUT 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition, Figure A. REV. 1.1 April 2001 V62C2161024L(L) V62C2161024L( measured from the beginning WP ...
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... All read cycle timings are referenced from the last valid address to the first transtion address. 10 must be HIGH during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.1 April 2001 V62C2161024L(L) (L Version Only) Symbol ...
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... Ordering Information Device Type* V62C2161024L-55T V62C2161024L-70T V62C2161024L-85T V62C2161024L-100T V62C2161024LL-55T V62C2161024LL-70T V62C2161024LL-85T V62C2161024LL-100T * For Industrial temperature tested devices, an “I” designator will be added to the end of the device number. REV. 1.1 April 2001 V62C2161024L(L) Speed Package 55 ns 44-pin TSOP Type 100 ...
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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V62C2161024L(L) UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE ...