V62C1162048L-100B MOSEL [Mosel Vitelic, Corp], V62C1162048L-100B Datasheet
V62C1162048L-100B
Related parts for V62C1162048L-100B
V62C1162048L-100B Summary of contents
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... BHE BLE CE REV. 1.2 May 2001 V62C1162048L(L) Functional Description The V62C1162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy Memory expansion is provided by an active LOW (CE) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed ...
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... MOSEL VITELIC V62C1162048L(L Top View 48 Ball - BGA (Ultra Low Power REV. 1.2 May 2001 V62C1162048L( aaa SIDE VIEW BOTTOM VIEW SOLDER BALL 2 V62C1162048L( BLE OE A0 ...
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... Key Don’t Care Low High Recommended Operating Conditions Parameter Supply Voltage Input Voltage * V min = -2.0V for pulse width less than For Industrial Temperature REV. 1.2 May 2001 V62C1162048L(L) Symbol Vt PT Tstg Tbias BLE BHE I/O1-I/O8 I/O9-I/O16 X X High-Z High Data Out ...
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... AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 70ns/85ns Load for 100ns/120ns REV. 1.2 May 2001 V62C1162048L(L) (V =1.8 to 2.2V, Gnd = 0V Test Conditions Sym Min Max Min Max Min Max Min Max I ...
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... Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End BLE, BHE Setup to Write End REV. 1.2 May 2001 V62C1162048L(L) = 1.8 to 2.2V, Gnd = 0V Sym -70 Min Max Min Max Min Max Min Max ...
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... Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with Address valid prior to coincident with CE transition Low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition, Figure A. REV. 1.2 May 2001 V62C1162048L( ...
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... Address CE BLE/BHE WE Data In Data Out Timing Waveform of Write Cycle 2 (CE Controlled) Address CE BLE/BHE WE Data In Data Out Timing Waveform of Write Cycle 3 (BLE/BHE Controlled) Address CE BLE/BHE WE Data In Data Out REV. 1.2 May 2001 V62C1162048L( ( (4) High-Z t OHZ ( ...
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... OUT 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition, Figure A. REV. 1.2 May 2001 V62C1162048L(L) V62C1162048L( measured from the beginning WP ...
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... All read cycle timings are referenced from the last valid address to the first transtion address. 10 must be HIGH during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.2 May 2001 V62C1162048L(L) (L Version Only) Symbol ...
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... V62C1162048L(L)-100B V62C1162048L(L)-120B V62C1162048L(L)-70M V62C1162048L(L)-85M V62C1162048L(L)-100M V62C1162048L(L)-120M * For Industrial temperature tested devices, an “I” designator will be added to the end of the device number. REV. 1.2 May 2001 V62C1162048L(L) Speed Package 70 ns 44-pin TSOP Type 100 ns 120 ...
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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V62C1162048L(L) UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE ...