V62C1802048L-100T MOSEL [Mosel Vitelic, Corp], V62C1802048L-100T Datasheet
V62C1802048L-100T
Related parts for V62C1802048L-100T
V62C1802048L-100T Summary of contents
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... REV. 1.2 May 2001 V62C1802048L(L) Functional Description The V62C1802048L is a low power CMOS Static RAM orga- nized as 262,144 words by 8 bits. Easy memory expansion is p- rovided by an active LOW CE1 , an active HIGH CE2, an act- (CMOS input/output) ive LOW OE , and Tri-state I/O’s. This device has an auto- matic power-down mode feature when deselected ...
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... Key Don’t Care Low High Recommended Operating Conditions Parameter Supply Voltage Input Voltage * V min = -1.0V for pulse width less than For Industrial Temperature. REV. 1.2 May 2001 V62C1802048L(L) Symbol Minimum Tstg Tbias WE OE Data X X High High-Z ...
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... This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 70ns/ Load 100ns/150 ns C REV. 1.2 May 2001 V62C1802048L( 1.8 to 2.2V, Gnd = 0V Test Conditions Sym Max, I ...
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... Address Setup Time Write Pulse Width Write Recovering Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End REV. 1.2 May 2001 V62C1802048L( 1.8 to2.2V, Gnd = 0V Symbol -70 Min Max Min Max Min Max Min Max ...
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... Timing Waveform of Read Cycle 1 Address D OUT Timing Waveform of Read Cycle 2 CE1 OE D OUT Supply Current Timing Waveform of Read Cycle 3 CE2 OE D OUT Supply Current REV. 1.2 May 2001 V62C1802048L(L) (3,6,7,9) (Address Controlled Data Valid (5,6,8,9) (CE1 Controlled OLZ t ACE ...
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... Timing Waveform of Write Cycle 1 Address OUT Timing Waveform of Write Cycle 2 Address CE1 OUT Timing Waveform of Write Cycle 3 Address CE2 OUT REV. 1.2 May 2001 V62C1802048L(L) (10,11) (WE Controlled Data Valid t WZ (10,11) (CE1 Controlled ...
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... All read cycle timings are referenced from the last valid address to the first transtion address. 10. CE1 or WE must be HIGH or CE2 must be LOW during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.2 May 2001 V62C1802048L(L) (L Version Only) Symbol ...
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... Device Type* V62C1802048L-70V V62C1802048L-85V V62C1802048L-100V V62C1802048L-150V V62C1802048LL-70V V62C1802048LL-85V V62C1802048LL-10 0V V62C1802048LL-150V V62C1802048L-70T V62C1802048L-85T V62C1802048L-100T V62C1802048L-150T V62C1802048LL-70T V62C1802048LL-85T V62C1802048LL-100T V62C1802048LL-150T * For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device number. REV. 1.2 May 2001 V62C1802048L(L) Speed Package 70 ns 8x13.4 mm 32-pin Plastic STSOP ...
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... If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. V62C1802048L(L) UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE ...