V62C21164096L-70B MOSEL [Mosel Vitelic, Corp], V62C21164096L-70B Datasheet - Page 8

• Manufacturer Part Number: V62C21164096L-70B
• Description: 256K x 16, 0.20 um CMOS STATIC RAM
• Manufacturer: MOSEL [Mosel Vitelic, Corp]

M O S E L V I T E L I C
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
Write Cycle 2 (CE Controlled)
NOTES:
1.
2.
3.
4.
5.
6.
7.
V62C21164096 Rev. 1.6 October 2001
The internal write time of the memory is defined by the overlap of CE
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
t
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
OE = V
If CE
to the outputs must not be applied to them.
t
CE
WR
CW
2
is measured from the earlier of CE
is measured from CE
is available on BGA package only.
1
is LOW and CE
IL
ADDRESS
ADDRESS
or V
OUTPUT
OUTPUT
INPUT
INPUT
IH
. However it is recommended to keep OE at V
CE
CE
CE
CE
WE
WE
1
2
1
2
2
is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
1
going low or CE
High-Z
(4, 7)
(4, 7)
1
or WE going high, or CE
2
t
AS
going HIGH to the end of write.
t
AS
t
t
WHZ
AW
(4)
t
WC
IH
8
t
AW
t
t
during write cycle to avoid bus contention.
CW
CW
2
t
t
CW
CW
going LOW at the end of the write cycle.
t
WC
(6)
(6)
1
(6)
(6)
t
and CE
WP
(1)
t
DW
2
t
DW
active and WE low. All signals must be active to
t
DH
t
WR
t
DH
(2)
(5)
t
WR
V62C21164096
(2)