IP4855CX25 NXP [NXP Semiconductors], IP4855CX25 Datasheet - Page 18

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IP4855CX25

Manufacturer Part Number
IP4855CX25
Description
SD 3.0-compliant memory card integrated voltage level translator with EMI filter and ESD protection
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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NXP Semiconductors
IP4855CX25
Product data sheet
Fig 10. DDR50 write timing diagram
13.3 DDR50 mode timing details
The Default-Speed (DS) and High-Speed (HS) modes use 3.3 V signaling and offer a
maximum of 25 MB/s. Besides these modes, IP4855CX25 also supports the SDR12,
SDR25 and DDR50 modes using 1.8 V signaling and up to 50 MB/s.
Especially the DDR50 mode introduces a basic change in the timing behavior of the
SD card interface. The SDR12 and SDR50 modes are similar to the DS and HS modes.
Any delay on all relevant signal lines (as shown in the timing diagram in
uncritical for SD card write operations as long as the skew between the different signals is
small enough.
SD 3.0-compliant memory card integrated dual voltage level translator
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
,3&;
IP4855CX25
© NXP B.V. 2012. All rights reserved.
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