IP4855CX25 NXP [NXP Semiconductors], IP4855CX25 Datasheet - Page 19

• Manufacturer Part Number: IP4855CX25
• Description: SD 3.0-compliant memory card integrated voltage level translator with EMI filter and ESD protection
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
IP4855CX25
Product data sheet
In contrast to the write cycle, the read cycle is more complex to analyze and depends on
the IP4855CX25 delay, the maximum delay added by the PCB and the additional setup
time of the SD card.
Table 15.
The same mechanism is triggered on each falling clock edge too, as the DDR50 mode
uses both edges of the clock signal for data transfer.
According to the SD 3.01 physical layer specification, the maximum delay between
CLK_IN (CLK_SD signal) at the SD card and data out from the SD card (DATA[3:0]_SD
out) is 7.0 ns. This value is specified for a load of C
Parameter
Symmetrical trace length
t
Driver model
PCB output impedance Z
PD
DDR50 read mode: parameters for best case and worst case timings
SD 3.0-compliant memory card integrated dual voltage level translator
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
o
15 mm per side
Best case timing
65 
minimum
fast
(Figure
L
 25 pF.
11)
Worst case timing
25 
100 mm per side
maximum
slow
IP4855CX25
© NXP B.V. 2012. All rights reserved.
(Figure
19 of 29
12)