CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 50

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

14.2 Hardware Mode 1 Description
(DEFAULT Data Flow, AES3 Input)
Hardware Mode 1 data flow is shown in Figure 26.
Audio data is input via the AES3 receiver, and rate
converted. The audio data at the new rate is then
output both via the serial audio output port and via
the AES3 transmitter.
The channel status data, user data and validity bit
information are handled in 2 alternative modes: 1A
and 1B, determined by a start-up resistor on the
COPY pin. In mode 1A, the received PRO, COPY,
ORIG, EMPH, and AUDIO channel status bits are
output on pins. The transmitted channel status bits
are copied from the received channel status data,
and the transmitted U and V bits are 0.
In mode 1B, only the COPY and ORIG pins are
output, and reflect the received channel status data.
The transmitted channel status bits, user data and
validity bits are input serially via the PRO/C, EM-
PH/U and AUDIO/V pins. Figure 22 shows the
timing requirements.
50
RXP
RXN
RMCK
Power supply pins (VD+, VA+, DGND, AGND), the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 26. Hardware Mode 1 - Default Data Flow, AES3 Input
AES3 Rx
&
Decoder
DFC0
RERR
MUTE
DFC1
Clocked by
Input Derived Clock
PRO/C
S/AES
COPY ORIG EMPH/U
Sample
Rate
Converter
VD+
C & U bit Data Buffer
Clocked by
Output Clock
Start-up options are shown in Table 6, and allow
choice of the serial audio output port as a master or
slave, choice of 4 serial audio output port formats,
and the source for transmitted C, U and V data. The
following pages contain the detailed pin descrip-
tions for hardware mode 1.
If a validity, parity, bi-phase or lock receiver error
occurs, the current audio sample will be held.
H/S
SDOUT RMCK RERR COPY
LO
HI
-
-
-
-
-
-
Table 6. Hardware Mode 1 Start-up Options
LO
LO
HI
HI
-
-
-
-
LO
LO
HI
HI
AUDIO/V TCBL
-
-
-
-
Output
Clock
Source
AES3
Encoder
& Tx
Serial
Audio
Output
OMCK
LO
HI
-
-
Serial Output Port is Slave
Serial Output Port is Master
Mode1A: C transmitted data
is copied from received data,
U & V = 0, received PRO,
EMPH, AUDIO are visible.
Mode 1B: CUV transmitted
data is input serially on pins,
received PRO, EMPH,
AUDIO are not visible
Serial Output Format OF1
Serial Output Format OF2
Serial Output Format OF3
Serial Output Format OF4
TXP
TXN
TCBLD
OLRCK
OSCLK
SDOUT
Function
CS8420
DS245PP2