CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 38

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CS8420

Manufacturer Part Number
CS8420
Description
DIGITAL AUDIO SAMPLE RATE CONVERTER
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet

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11.12 Interrupt 2 Register Mask (12)
11.13 Interrupt Register 2 Mode Registers MSB & LSB(13,14)
38
7
0
7
0
0
The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error
is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If
a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the
INT pin or the status register. The bit positions align with the corresponding bits in Interrupt Register
2. This register defaults to 00.
The two Interrupt Mode registers form a 2-bit code for each Interrupt 2 register function. This code
determines whether the INT pin is set active on the arrival of the interrupt condition, on the removal
of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers
default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6
0
6
0
0
VFIFOM
VFIFO1
VFIFO0
5
5
REUNLOCKM
REUNLOCK1
REUNLOCK0
4
4
DETUM
DETU1
DETU0
3
3
EFTUM
EFTU1
EFTU0
2
2
QCHM
QCH1
QCH0
1
1
CS8420
DS245PP2
UOVWM
UOVW1
UOVW0
0
0

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