CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 36

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

11.8
TSLIP
OSLIP
SRE
OVRGL
OVRGR
DETC
EFTC
RERR
36
TSLIP
7
Interrupt 1 Register Status (7) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once
since the register was last read. A ”0” means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be “0” in this register. This register defaults to 00.
OSLIP
clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time
a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not
in use, this bit will go high on receipt of a new TCBL signal.
and OLRCK is asynchronous to the port data source, this bit will go high every time a data sam-
ple is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output
serial port configured in slave mode, this bit will indicate if the ratio of OMCK frequency to OL-
RCK frequency does not match what is set in the CLK1 and CLK0 bits.
channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full-scale.
channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full-scale
in the C bit buffer management process.
in the C bit buffer management process.
of the error which caused the interrupt.
AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which
Serial audio output port data slip interrupt. When the serial audio output port is in slave mode,
Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3.
Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left
Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right
D to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer
E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer
A receiver error has occurred. The Receiver Error register may be read to determine the nature
6
SRE
5
OVRGL
4
OVRGR
3
DETC
2
EFTC
1
CS8420
DS245PP2
RERR
0