HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 861

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the
T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus outputs are held during the T3 state.The same timing applies when a reset
occurs in the T2 state of an access cycle to a two-state-access area.
ø
RES
Internal
reset signal
Address bus
CS
CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
to CS
1
Figure D-3 Reset during Memory Access (Reset during T3 State)
Access to external address
T1
854
T2
T3
High impedance
High impedance
High impedance
H'000000