SAK-XC2264-56F66L INFINEON [Infineon Technologies AG], SAK-XC2264-56F66L Datasheet - Page 92

• Manufacturer Part Number: SAK-XC2264-56F66L
• Description: 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
Table 23
Parameter
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
BHE, ALE
Output valid delay for:
A23 … A16, A15 … A0 (on P0/P1)
Output valid delay for:
A15 … A0 (on P2/P10)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on P2/P10)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
READY, D15 … D0 (read data)
Input hold time for:
READY, D15 … D0 (read data)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
Data Sheet
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
External Bus Cycle Timing for 3.0 V ≤
(Operating Conditions apply)
1)
Symbol
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
10
11
12
13
14
15
16
20
21
23
24
25
30
31
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
90
Min.
–
–
–
–
–
–
–
0
0
0
0
0
29
-6
V
Limits
XC2000 Family Derivatives
Typ.
DDP
≤ 4.5 V
Max.
20
20
22
22
20
21
21
10
10
10
10
10
–
–
Electrical Parameters
XC2267 / XC2264
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V0.1, 2007-02
Draft Version
Note