SAK-XC2264-56F66L INFINEON [Infineon Technologies AG], SAK-XC2264-56F66L Datasheet - Page 30

• Manufacturer Part Number: SAK-XC2264-56F66L
• Description: 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
3
The architecture of the XC226x combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see
by enabling the concurrent operation of several subsystems of the XC226x.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC226x.
Figure 3
Data Sheet
Oscillators/PLL, System Fct.
ADC1
10-Bit
8-Bit/
8 Ch.
P15
Clock, Reset, Power Control,
Program Flash 0
Program Flash 1
Program Flash 2
16/32/64 Kbytes
0/64/256 Kbytes
192/256 Kbytes
5
256 Kbytes
Functional Description
PSRAM
16 Ch.
Stand-By RAM
ADC0
10-Bit
8-Bit/
Block Diagram
Port 5
Figure
11
BRGen
GPT
T2
T3
T4
T5
T6
3). This bus structure enhances the overall system performance
CC2
T7
T8
P10
2 Kbytes
CCU63
DPRAM
T12
T13
16
Interrupt Bus
C166SV2 - Core
...
Interrupt & PEC
CCU60
CPU
28
T12
T13
16 Kbytes
P7 P6
DSRAM
5
3
RS232,
USIC2
IIC, IIS
2 Ch.,
Buffer
64 x
XC2000 Family Derivatives
LIN,
SPI,
P4
4
USIC1
RS232,
IIC, IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
Functional Description
MC_XC226X_BLOCKDIAGRAM
XC2267 / XC2264
USIC0
RS232,
2 Ch.,
Buffer
IIC, IIS
P2
64 x
LIN,
SPI,
WDT
Debug Support
RTC
13
LXBus Control
External Bus
Control
OCDS
EBC
P1
M ulti
CAN
5 ch.
V0.1, 2007-02
Draft Version
8
P0
8