SSTUB32866EC/S NXP [NXP Semiconductors], SSTUB32866EC/S Datasheet - Page 16

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SSTUB32866EC/S

Manufacturer Part Number
SSTUB32866EC/S
Description
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
SSTUB32866_4
Product data sheet
Fig 9.
(not used)
PAR_IN
RESET
QERR
DCS
CSR
PPO
(1) PAR_IN is driven from PPO of the first SSTUB32866 device.
Q14
D14
CK
CK
D1
Q1
to
to
(1)
C0 = 1, C1 = 1
Timing diagram for the second SSTUB32866 (1 : 2 Register B configuration) device used in pair;
CK to Q
t
PD
t
su
m
All information provided in this document is subject to legal disclaimers.
t
h
Rev. 04 — 15 April 2010
1.8 V DDR2-800 configurable registered buffer with parity
m + 1
CK to QERR
CK to PPO
t
t
PD
PD
t
su
m + 2
t
h
m + 3
SSTUB32866
CK to QERR
t
PD
© NXP B.V. 2010. All rights reserved.
m + 4
002aaa657
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