ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 43

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4921C–AUTO–01/07
Table 4-2.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
• Bit 2 – EEMPE: EEPROM Master Write Enable
• Bit 1 – EEPE: EEPROM Write Enable
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
EEPM1
The Programming times for the different modes are shown in
any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writ-
ing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at
the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See
the description of the EEPE bit for an EEPROM write procedure.
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE,
otherwise no EEPROM write takes place. The following procedure should be followed when
writing the EEPROM (the order of steps 3 and 4 is not essential):
The EEPROM can not be programmed during a CPU write to the Flash memory. The soft-
ware must check that the Flash programming is completed before initiating a new EEPROM
write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to pro-
gram the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
“Boot Loader Support – Read-While-Write Self-Programming, ATA6602 and ATA6603” on
page 281
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM
is interrupting another EEPROM access, the EEAR or EEDR Register will be modified,
causing the interrupted EEPROM access to fail. It is recommended to have the Global Inter-
rupt Flag cleared during all the steps to avoid these problems.
0
0
1
1
EEPM0
for details about Boot programming.
EEPROM Mode Bits
0
1
0
1
Programming
3.4 ms
1.8 ms
1.8 ms
Time
–
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
ATA6602/ATA6603
Table
4-2. While EEPE is set,
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