ADM1041ARQ AD [Analog Devices], ADM1041ARQ Datasheet - Page 8

• Manufacturer Part Number: ADM1041ARQ
• Description: Secondary-Side Controller with Current Share and Housekeeping
• Manufacturer: AD [Analog Devices]

ADM1041
Parameter
CURRENT SENSE CALIBRATION
SHARE BUS OFFSET
CURRENT TRANSFORMER SENSE INPUT, I
DC Offset Trim Range (with respect to input)
DC Offset Trim Step Size
(with respect to input)
Gain Range (I
Gain Setting 1 (Reg 16h[2:0] = 000)
Gain Setting 2 (Reg 16h[2:0] = 001)
Gain Setting 3 (Reg 16h[2:0] = 010)
Gain Setting 4 (Reg 16h[2:0] = 100)
Gain Setting 5 (Reg 16h[2:0] = 101)
Gain Setting 6 (Reg 16h[2:0] = 110)
Full Scale (No Offset)
Current Share Trim Step (at SHRO)
Gain Accuracy
Gain Accuracy
Gain Accuracy
Current Share Offset Range
Zero Current Offset Trim Step
Gain Setting 0
Gain Setting 1
CT Input Sensitivity
CT Input Sensitivity
Input Impedance
Source Current
Source Current Step Size
Reverse Current for Extended SMBus
Total Current Sense Error
(Gain and Offset)
Attenuation Range
Addressing (Source Current)
SENSE
2, 4
2, 4
2, 4
, 40 mV at C
, 20 mV at C
, 40 mV at C
)
2
2
S
S
S
+, C
+, C
+, C
5
S
S
S
−
−
–
CT
Min
−5
−5
−2.5
1.25
0.45
0.79
20
3.5
Rev. A | Page 8 of 64
Typ
−8
−15
−30
8
15
30
30
50
120
±3
±6
65
85
110
135
175
230
2.0
65 to 99
0.4
8
±1
±0.5
0.4
5.5
4.5
2.57
0.5
1.0
50
2.0
170
5
Max
+5
+5
+2.5
0.68
1.20
7
Unit
mV
mV
mV
mV
mV
mV
µV
µV
µV
%
%
V/V
V/V
V/V
V/V
V/V
V/V
V
%
%
mV
%
%
%
V
%
mV
V/V
V/V
V
V
kΩ
µA
nA
mA
Test Conditions/Comments
Reg 17h[2:0] = 000. See Table 32 .
Reg 17h[2:0] = 001. See Table 32.
Reg 17h[2:0] = 010. See Table 32.
Reg 17h[2:0] = 100. See Table 32.
Reg 17h[2:0] = 101. See Table 32.
Reg 17h[2:0] = 110. See Table 32.
V
8 bits, 255 steps
Reg 15h[7:0]. See Table 30.
V
SHRO = 2 V. Gain = 230x
Chopper ON
Chopper OFF
Input voltage range at C
34.0 mV – 44.5 mV. Gain = 65×
26.0 mV – 34.0 mV. Gain = 85×
20.0 mV – 26.0 mV. Gain = 110×
16.0 mV – 20.0 mV. Gain = 135×
12.0 mV – 16.0 mV. Gain = 175×
9.5 mV – 12.0 mV. Gain = 230×
V
Reg 06h[7:1]. See Table 15.
SHRS = SHRO = 1 V
7 bits, 127 steps I
0 V ≤ V
V
V
Gain = 135×
V
Gain = 65×
See Figure 13.
Reg 17h[7] = 1. See Table 32.
Reg 17h[5] = 1. See Table 32.
0 ≤ V
8 bits, 255 steps, V
Reg 05h[7:0]. See Table 14.
Reg 17h[7] = 1. See Table 32.
Reg 06h = FEh. See Table 15.
Reg 17h[5] = 0, V
Reg 17h[5] = 1. See Table 32.
Reg 15h = 05h, approx 1 µA.
See Table 30. V
Gain setting = 4.5
Gain setting = 2.57
See Current Transformer Input
Section.
15 steps Reg 15h[3:0].
See Table 30.
See Figure 38. See Absolute
Maximum Ratings.
CM
CSCM
ZO
CSCM
CSCM
CSCM
= 0
= 2.0 V, V
TRIM
= 2.0V, 0°C ≤ T
= 2.0V, 0°C ≤ T
= 2.0 V, 0°C ≤ T
= Input Common Mode
CSCM
≤ 1.25 V
≤ 0.3 V. Gain = 65×
DIFF
SHARE
= 0 V
SHARE
SHARE
CT
A
A
= 2 V.
A
= 1.0 V
≤ 85°C
≤ 85
≤ 85°C
slope
= 2 V. Table 31
S
+, C
O
C SHRS =
S
−