ADM1041ARQ AD [Analog Devices], ADM1041ARQ Datasheet - Page 55

• Manufacturer Part Number: ADM1041ARQ
• Description: Secondary-Side Controller with Current Share and Housekeeping
• Manufacturer: AD [Analog Devices]

APPENDIX A—CONFIGURATION TABLE
This table is included for users to program the part by function, rather than by register.
Table 45.
Description
Chip address is 1010xxx.
Second address bit
(EEPROM programmable).
First address bit:
ADD0 = L, pin to ground.
ADD0 = H, pin to V
ADD0 = Z, pin open.
Broadcast address.
Config AC_OKLink and
PSONLink.
Configure AC
hardware derived or from
an SMBus command.
Configure PSON to be
hardware derived or from
an SMBus command.
Configure UV blanking to
be internally derived or
from AC_OKLink. (Set
opposite to i2cmb).
Build FAULT or SMBAIert
signal. Allows a composite
interrupt to be constructed
by ORing up to 15 different
signals.
This uses the CBD pin.
m_cbd_w is a µP writable
bit.
SENSE
to be
DD
.
Bit No.
1
0
6
7
4
7–0
7–1
Name
add1
i2cmb
up_AC_OK_m
up_pson_m
uvbm
selcbd1
selcbd2
Rev. A | Page 55 of 64
Bit
Bit
Bit
b1
0
0
0
1
1
1
X
b0
0
1
b6
0
1
b7
0
1
b4
0
1
bn
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Option
ADD0
L
H
Z
L
H
Z
X
Mode
Normal SMBus, microprocessor
SCL = AC_OK Link
SDA = PS
Mode
Hardware AC
Microprocessor support via SMBus
Mode
Hardware PS_ON
Micorporcessor support
via SMBus
Mode
UVB follows AC_OKLink
UVB follows AC
signal
ovfault
uvfault
ocpt0 (ridethough timed out)
acsnsb
ocpf
otp (mov5)
orfetokb
Share_OKb
V
mfgl
mfg2
mfg3
mfg4
m_cbd_w
mfg5
Not used
DD
OK b
ON
Link
SENSE
SENSE
xxx
000
001
100
010
011
101
111
Target
device
0
1
4
2
3
5
ALL
ADM1041