MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 380

no-image

MC68HC912DG128A

Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912DG128ACPV
Manufacturer:
FREESCALE
Quantity:
201
Part Number:
MC68HC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 000
Part Number:
MC68HC912DG128AMPV
Manufacturer:
FREESCALE
Quantity:
334
Part Number:
MC68HC912DG128AVPV
Manufacturer:
FUJI
Quantity:
6 629
Appendix B: CGM Practical Aspects
Practical Aspects For The PLL Usage
Synthesized Bus
Frequency
Operation Under
Adverse
Environmental
Conditions
MC68HC912DT128A Rev 2.0
380
NOTE:
Starting from a ceramic resonator or quartz crystal frequency F
‘refdv’ and ‘synr’ are the decimal content of the REFDV and SYNR
registers respectively, then the MCU bus frequency will simply be:
It is not allowed to synthesize a bus frequency that is lower than the
crystal frequency, as the correct functioning of some internal
synchronizers would be jeopardized (e.g. the MCLK and XCLK clock
generators).
The normal operation for the PLL is the so-called ‘automatic bandwidth
selection mode’ which is obtained by having the AUTO bit set in the
PLLCR register. When this mode is selected and as the VCO frequency
approaches its target, the charge pump current level will automatically
switch from a relatively high value of around 40 A to a lower value of
about 3 A. It can happen that this low level of charge pump current is
not enough to overcome leakages present at the XFC pin due to adverse
environmental conditions. These conditions are frequently encountered
for uncoated PCBs in automotive applications. The main symptom for
this failure is an unstable characteristic of the PLL which in fact ‘hunts’
between acquisition and tracking modes. It is then advised for the
running software to place the PLL in manual, forced acquisition mode by
clearing both the AUTO and the ACQ bits in the PLLCR register. Doing
so will maintain the high current level in the charge pump constantly and
will permit to sustain higher levels of leakages at the XFC pin. This latest
revision of the Clock Generator Module maintains the lock detection
feature even in manual bandwidth control, offering then to the
application software the same flexibility for the clocking control as the
automatic mode.
Appendix B: CGM Practical Aspects
F
BUS
=
synr
refdv
F
VCO
=
0,1,2,3...63}
0,1,2,3...7}
F
--------------------------------------------- -
XTAL
refdv
synr
+
1
+
1
MOTOROLA
XTAL
4-cgmpa
, if

Related parts for MC68HC912DG128A