MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 314

• Manufacturer Part Number: MC68HC912DG128A
• Description: microcontroller unit 16BIT DEVICE
• Manufacturer: MOTOROLA [Motorola, Inc]

Analog-To-Digital Converter (ATD)
MC68HC912DT128A Rev 2.0
314
AFFC — ATD Fast Flag Clear All
ASWAI — ATD Stops in Wait Mode
When the ASWAI bit is set and the module enters wait mode, most of the
clocks stop and the analog portion powers down. When the module
comes out of wait, it is recommended that a stabilization delay (stop and
ATD power up recovery time, t
started. Additionally, the ATD does not re-initialize automatically on
leaving wait mode.
DJM — Result Register Data Justification Mode
Software can disable the clock signal to the A/D converter and power
down the analog circuits to reduce power consumption. When reset
to zero, the ADPU bit aborts any conversion sequence in progress.
Because the bias currents to the analog circuits are turned off, the
ATD requires a period of recovery time to stabilize the analog circuits
after setting the ADPU bit.
0 = ATD flag clearing operates normally (read the status register
1 = Changes all ATD conversion complete flags to a fast clear
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
0 = Left justified
1 = Right justified
For 10-bit resolution, left justified mode maps a result register
into data bus bits 6 through 15; bit 15 is the MSB. In right justified
mode, the result registers maps onto data bus bits 0 through 9;
bit 9 is the MSB.
For 8-bit resolution, left justified mode maps a result into the high
byte (bits 8 though 15; bit 15 is the MSB). Right justified maps a
result into the low byte (bits 0 through 7; bit 7 is the MSB).
before reading the result register to clear the associated CCF
bit).
sequence. Any access to a result register (ATD0–7) will cause
the associated CCF flag to clear automatically if it was set at
the time.
Analog-To-Digital Converter (ATD)
SR
) is allowed before new conversions are
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