MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 204

• Manufacturer Part Number: MC68HC912DG128A
• Description: microcontroller unit 16BIT DEVICE
• Manufacturer: MOTOROLA [Motorola, Inc]

TFLG1 — Main Timer Interrupt Flag 1
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
204
RESET:
Bit 7
C7F
0
C6F
6
0
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the
use of the ICOVW register ($AA) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
C5F
5
0
Enhanced Capture Timer
PR2
0
0
0
0
1
1
1
1
C4F
4
0
Table 32 Prescaler Selection
PR1
0
0
1
1
0
0
1
1
C3F
3
0
PR0
C2F
0
1
0
1
0
1
0
1
2
0
Prescale Factor
C1F
1
0
128
16
32
64
1
2
4
8
Bit 0
C0F
0
MOTOROLA
$008E
18-ect