PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 84
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
- Current page: 84 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
REGISTER 8-2:
DS39682C-page 82
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
INTCON2: INTERRUPT CONTROL REGISTER 2
bit 7
Legend:
R = Readable bit
-n = Value at POR
Note:
R/W-1
RBPU
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software should
ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
INTEDG0
R/W-1
INTEDG1
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
INTEDG2
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
TMR0IP
R/W-1
© 2007 Microchip Technology Inc.
x = Bit is unknown
U-0
—
R/W-1
RBIP
bit 0
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