PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 279
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
- Current page: 279 of 358
- Download datasheet (6Mb)
SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example 1:
Example 2:
Example 3:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
W
C
Z
N
W
C
W
C
Z
N
W
C
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ‘k’
Subtract W from Literal
SUBLW k
0 ≤ k ≤ 255
k – (W) → W
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
1
1
SUBLW
SUBLW
SUBLW
Read
Q2
0000
01h
?
01h
1
0
0
02h
?
00h
1
1
0
03h
?
FFh ; (2’s complement)
0
0
1
; result is positive
; result is zero
; result is negative
02h
02h
02h
1000
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
Preliminary
PIC18F45J10 FAMILY
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
Subtract W from f
SUBWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – (W) → dest
N, OV, C, DC, Z
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 21.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
1
1
SUBWF
SUBWF
SUBWF
Read
Q2
0101
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
1
2
?
FFh ;(2’s complement)
2
0
0
1
; result is positive
; result is zero
; result is negative
f {,d {,a}}
REG, 1, 0
REG, 0, 0
REG, 1, 0
11da
Process
Data
Q3
DS39682C-page 277
ffff
destination
Write to
Q4
ffff
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