PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 100
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
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PIC18F45J10 FAMILY
TABLE 9-5:
DS39682C-page 98
RB0/INT0/FLT0/
AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
RB4/KBI0/AN11
RB5/KBI1/T0CKI/
C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
Pin
2:
3:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX configuration bit is ‘0’. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
PORTB I/O SUMMARY
Function
CCP2
C1OUT
T0CKI
AN12
AN10
AN11
FLT0
INT0
INT1
INT2
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB0
RB1
RB2
AN8
RB3
AN9
RB4
RB5
RB6
RB7
(2)
Setting
TRIS
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
0
1
1
1
0
1
1
1
0
0
1
1
x
0
1
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATB<0> data output; not affected by analog input.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
External interrupt 0 input.
PWM Fault input (ECCP1/CCP1 module); enabled in
software.
A/D input channel 12.
LATB<1> data output; not affected by analog input.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
External interrupt 1 input.
A/D input channel 10.
LATB<2> data output; not affected by analog input.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
External interrupt 2 input.
A/D input channel 8.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 9.
CCP2 compare and PWM output.
CCP2 capture input
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
Interrupt-on-change pin.
A/D input channel 11.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
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Description
© 2007 Microchip Technology Inc.
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