PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 112
![no-image](/images/no-image-200.jpg)
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
- Current page: 112 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
FIGURE 9-4:
FIGURE 9-5:
TABLE 9-13:
DS39682C-page 110
PORTD
LATD
TRISD
PORTE
LATE
TRISE
INTCON
PIR1
PIE1
IPR1
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1:
Name
PORTD<7:0>
PORTD<7:0>
(1)
(1)
(1)
(1)
(1)
(1)
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
PSPIF
PSPIF
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
GIE/GIEH PEIE/GIEL
OBF
PSPIE
PSPIP
PSPIF
OBF
CS
WR
RD
IBF
CS
WR
RD
IBF
Bit 7
RD7
IBF
—
—
—
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
(1)
(1)
(1)
PARALLEL SLAVE PORT WRITE WAVEFORMS
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q1
ADIF
ADIE
ADIP
Bit 6
RD6
OBF
—
—
—
Q2
Q2
TMR0IE
VCFG1
IBOV
RCIF
RCIE
RCIP
Bit 5
RD5
Q3
Q3
—
—
Q4
Q4
PSPMODE
VCFG0
INT0IE
Preliminary
TXIE
TXIP
Bit 4
TXIF
RD4
—
—
Q1
Q1
SSP1IF
SSP1IE
SSP1IP
PCFG3
Q2
Q2
RBIE
Bit 3
RD3
—
—
—
Q3
Q3
PORTE Data Latch Register
(Read and Write to Data Latch)
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
Bit 2
RD2
RE2
Q4
Q4
TMR2IF
TMR2IE
TMR2IP
TRISE1
PCFG1
INT0IF
Q1
Q1
Bit 1
© 2007 Microchip Technology Inc.
RD1
RE1
Q2
Q2
TMR1IF
TMR1IE
TMR1IP
TRISE0
PCFG0
RBIF
Bit 0
RD0
RE0
Q3
Q3
on page
Values
Reset
Q4
Q4
46
46
46
46
46
46
43
45
45
45
44
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