PIC18F248-E/L MICROCHIP [Microchip Technology], PIC18F248-E/L Datasheet - Page 254

• Manufacturer Part Number: PIC18F248-E/L
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 21-3:
21.6
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS41159E-page 252
PIC18FXX8
Comparator Interrupts
COMPARATOR OUTPUT BLOCK DIAGRAM
Set
CMIF
bit
To RE1 or
RE2 pin
Bus
Data
Read CMCON
From
Other
Comparator
Q
Q
EN
D
CL
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
EN
Note:
D
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
Reset
Read CMCON
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
MULTIPLEX
Port Pins
+
-
© 2006 Microchip Technology Inc.
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