AT83C24NDS-PRRUM ATMEL [ATMEL Corporation], AT83C24NDS-PRRUM Datasheet - Page 16

• Manufacturer Part Number: AT83C24NDS-PRRUM
• Description: Smart Card Reader Interface with Power Management
• Manufacturer: ATMEL [ATMEL Corporation]

Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0
Deactivation Sequence
16
AT83C24
ISO 7816 constraints: ta = 200 card clock cycles
Note:
The activation sequence is controlled by software using TWI commands, depending on the
cards to support. For ISO 7816 cards, the following sequence can be applied:
Note:
Note:
The card automatic deactivation is triggered when one the following condition occurs:
•
Figure 12. Software activation without automatic control (ART bit = 0)
1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0
2. Wait of the end of the DC/DC init with a polling on VCARDOK bit (STATUS register)
3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have the
4. CRST pin is controlled by software using CARDRST bit (see INTERFACE register).
ICARDERR bit is set by hardware
Timer[1-0] reset value is 400.
register). This writing starts the DC/DC.
or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register).
When VCARDOK bit is set (by hardware), CARDIO bit should be set by software.
clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8
pins according to each other.
It is assumed that initially VCARD[1:0], CARDCK, CARDIO and CARDRST bits are cleared,
CKSTOP and IODIS are set (those bits are further explained in the registers description)
The user should check the AT83C24 status and possibly resume the activation sequence if one
TWI transfer is not acknowledged during the activation sequence.
CCLK
CRST
CVCC
CIO
400 card clock cycles< = tb
400 card clock cycles< = tc < = 40000 card clock cycles
1
2
3
4
ATR
4234F–SCR–10/05