AT83C24-PRTIL Atmel, AT83C24-PRTIL Datasheet
AT83C24-PRTIL
Specifications of AT83C24-PRTIL
Related parts for AT83C24-PRTIL
AT83C24-PRTIL Summary of contents
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... The AT83C24B is a smart card reader interface IC for smart card reader/writer appli- cations such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host AT83C24 can be connected in parallel using the programmable TWI address. Its high efficiency DC/DC converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications ...
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... MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus Block Diagram DVCC EVCC RESET PRES/ INT A2/CK, A1/RST, A0/3V, CMDVCC SCL SDA CLK I/O, C4, C8 AT83C24 2 VCC VSS Voltage supervisor POR/PFD Main TWI Control Controller & Logic Unit Clocks Controller ...
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... Remark: during power up and before registers configuration, the PRES/INT signal must be ignored. Microcontroller Interface Function: • Power-on reset • A low level on this pin keeps the AT83C24 under reset even if applied on power-on. It also resets the AT83C24 if applied when the AT83C24 is running (see Power I/O monitoring §). 3 kV open- • ...
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... CLK EVCC CIO CVCC CC4 CVCC CC8 CVCC CPRES VCC CCLK CVCC CRST CVCC CMDVCC EVCC VCC LI AT83C24 4 ESD Pad Type Description I Microcontroller Interface Function open- TWI serial data drain I Microcontroller Interface Function open- TWI serial clock drain Microcontroller Interface Function Copy of CIO pin and high level reference for EVCC ...
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... DC/DC Ground 8 kV+ GND CVSS is used to sink high shunt currents from the external coil. GND Ground ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses generated according to Mil/STD 883 Class3. Recommended capacitors soldered on CVCC and VCC pins. AT83C24 5 ...
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... Frame Structure The structure of the TWI bus data frames is made of one or a series of write and read com- mands completed by STOP. Write commands to the AT83C24 have the structure: ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S) Read commands to the AT83C24 have the structure: ADDRESS BYTE + DATA BYTE(S) The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset (hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset ...
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... If A2/CK to A0/3V are tied to the host microcontroller and their reset values are unknown, a gen- eral call on the TWI bus allows to reset all the AT83C24 devices and set their address after A2/CK to A0/3V are fixed. ...
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... Program the interface. This is a one-byte command. The MSB of the command byte is fixed General Call Reset: A general call followed by the value 06h has the same effect as a Reset command. Table 3. Write Commands Description 1. Reset 2. Write config 3. Write Timer 4. Write Interface 5. General Call Reset AT83C24 ...
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... PRES/INT pin to high level. Several AT83C24 devices can share the same interrupt and the microcontroller can identify the interrupt sources by polling the status of the AT83C24 devices using TWI commands. • If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing ...
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... Pull-up Card Contact Presence VSS CPRES VCC Card Contact Presence PRES/INT External Pull-down VSS AT83C24 10 over-current detection on CVCC VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software) VCC (See Table 18) Internal Pull-up PULLUP Bit = 1 Closed = 0 Open EVCC = 1 Closed ...
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... CCLK: Four different sources can be used: CLK pin, DCCLK signal, CARDCK bit or A2/CK pin (in transparent mode clock for DC/DC converter. 4234G–SCR–01/07 I/O EVCC CARDIO bit C4 EVCC CARDC4 bit C8 CARDC8 bit AT83C24 CVCC 0 CIO 1 CVCC 0 CC4 1 CVCC 0 CC8 ...
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... If the CRST pin signal is driven by the CARDRST bit value, two modes are available: • If the ART bit is reset, CRST pin is driven by CARDRST bit. • If the ART bit is set, CRST pin is controlled and follows the “Automatic Reset Transition” (page 15). AT83C24 12 CLK DCK[2:0] CKS[2:0] A2/CK ...
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... Figure 8. CRST Block Diagram with soft activation Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used) CMDVCC 4234G–SCR–01/07 CARDRST bit tb delay see Fig 12 CARDRST bit A1/RST CRST_SEL bit = 1 CMDVCC ART bit 1 CRST_SEL bit = ART bit 1 Hardware activation deactivation activation AT83C24 CRST CRST 13 ...
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... DCCLK signal, CLK signal , A2/CK signals or CARDCK bit (see Figures 5). • CRST signal is linked with A1/RST pin as soon as A1/RST pin level rising edge on A1/RST pin set the CRST pin. Note: Figure 10. Activation sequence with CMDVCC Note: AT83C24 14 1. The card must be deactivated to change the voltage. CMDVCC A1/RST CCLK CVCC ...
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... PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit should be set by software. clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8 pins according to each other. CARDRST bit set CVCC 3 1 CRST CCLK CIO AT83C24 ...
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... Timer[1-0] reset value is 400. Warm reset The AT83C24 offers a simple and accurate way to control the CRST signal during a warm reset. After an activation sequence (cold reset), a warm reset is started with a low level on CRST dur- ing a define delay (between 40000 and 45000 clock cycles for example). ...
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... It is assumed that initially VCARD[1:0], CARDCK, CARDIO and CARDRST bits are cleared, CKSTOP and IODIS are set (those bits are further explained in the registers description) The user should check the AT83C24 status and possibly resume the activation sequence if one TWI transfer is not acknowledged during the activation sequence. ...
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... Td equal to 8 periods of the DC/DC clock, typically 2 µs: 1. T0: CARDRST is cleared, SHUTDOWN bit set Td:CARDCK is cleared, CKSTOP, CARDIO and IODIS are set Td: CARDIO is cleared Td: VCARD[1-0] = 00. Figure 14. Deactivation Sequence Notes: AT83C24 18 CVCC CRST CCLK CIO, CC4, CC8 t1 1 ...
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... CRST pin. CKS in CONFIG2 allows to select standard or transparent configuration for the CCLK pin. So CCLK and CRST are independent. A2/CK to A0/3V inputs always give the TWI address at reset. The A0/3V pin can be used for TWI addressing and easily connect two AT83C24 devices on the same TWI bus. ...
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... If EVCC and VCC have the same value, then they should be connected: The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC supply. The bit powermon allows the user to select if the internal PFD monitors VCC or the internal regu- lated 3V. If the PFD monitors VCC (POWERMON bit=0), a deactivation is performed if VCC falls below VPFDP (see VPFDP value in the datasheet) ...
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... VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/ card is detected. VCARD[1:0] writing to 0 stops the DC/DC. No card deactivation is performed when the voltage is changed between 1.8V 5V. The microcontroller should deactivate the card before changing the voltage. The reset value is 00 INSERT ICARDERR VCARDERR AT83C24 1 0 VCARD1 VCARD0 21 ...
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... When CDS[2- and IT_SEL = 0, PRES/INT = 1 when no card is present and PRES/INT = 0 when a card is inserted even if CLK is STOPPED. This can be used to wake up the external microcontroller and restart CLK when a card is inserted in the AT83C24. If CDS[2- IT_SEL = 1 and CLK is stopped, a card insertion or extraction has no effect on PRES/INT pin. 4 ...
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... The user can’t directly select A2 or A2/2 after a reset or when switching from CKS = ( CKS = (4, 5). To select A2, the user should select A2/2 first and after A2. To select A2/2, the user should select A2 first and after A2/ DCK0 X CKS2 CKS1 AT83C24 1 0 CKS0 23 ...
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... X EVCC voltage is the level detected on I/O input pin. VEXT0 if EVCC is supplied from the external EVCC pin, the user can switch off the internal EVCC regulator to decrease the consumption. If EVCC is switched off, and no external EVCC is supplied, the AT83C24 is inactive until a hardware reset is done. The reset value is 100. CI ...
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... Clear this bit to deactivate the internal pull-up. PRES/INT is an open drain output with a programmable internal pull up. The reset value is 0. Power monitor Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24. 2 POWERMON Clear this bit to monitor any glitch on VCC. ...
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... Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put I/O, C4 Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or 6 IODIS power-down modes) ...
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... Card I/O 0 CIO This bit provides the actual level on the CIO pin when read. The reset value Bit 15 Bit 14 Bit 13 Bit Bit Mnemonic Description Bits Timer MSB (bits VCARDOK X VCARD_INT Bit 12 Bit 11 Bit 10 AT83C24 1 0 CRST CIO 1 0 Bit 9 Bit 8 27 ...
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... Table 14. TIMER 0 (Timer LSB) Number Reset value = 0x10010000 Table 15. CAPTURE 1 (Capture MSB) Number Reset value = 0x00000000 Table 16. CAPTURE 0 (Capture LSB) Number Reset value = 0x00000000 AT83C24 Bit 7 Bit 6 Bit 5 Bit Bit Mnemonic Description bits Timer LSB (bits 7to bit 15 bit 14 bit 13 Bit ...
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... EVCC connected to host power supply: from 1.6V to 5.5V -40°C to +85° CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24B CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Table 17 ...
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... PRES/INT weak pull-up output current PRES/INT EVCC EVCC pin not connected to a power supply EVCC EVCC pin connected to a power supply CLK Clock signal for AT83C24 CLK Clock signal for AT83C24NDS Table 19. Host Interface (SCL, SDA, RESET) Symbol Parameter V Input Low-voltage ...
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... AT83C24 Unit Test Conditions 0 < Icard < 60mA C =10µF L for AT83C24B mV 0 < Icard < 65mA C = 3.3µF L for AT83C24NDS Max. charge 40 nA.s V Max. duration 400 ns Max. Icard variation 200 mA V AT83C24B V AT83C24NDS > V Icard = 0, VCC PFDP µ ...
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... Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Table 23. Smart Card Clock (CCLK pin) Symbol Parameter V Output Low-voltage OL V Output High Voltage OH I Short Circuit Current Rise and Fall time R F AT83C24 32 Min Typ Max 140 250 110 250 130 250 100 250 Min Typ Max ...
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... CVCC CVCC 0.9 x CVCC CVCC -15 +15 -0.25 0.6 -0.25 0.4 -0.25 0.4 CVCC-0.5 CVCC+0.25 0.1 AT83C24 Unit Test Conditions CLASS A CCLK from 0.5 to 4.2V V/ns CLASS B CCLK from 0.5 to 0.85 x CVCC V CLASS A&B&C CVCC = CLASS A V CVCC = CLASS B CLASS C MHz ...
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... Parameter R CPRES weak pull-up output current CPRES Table 27. TWI (SDA, SCL pins) Symbol Parameter t Data set-up time SU;DAT t Data hold time HD;DAT t Fall time on SDA signal fDA AT83C24 34 Min Typ Max 0.12 x CVCC 0 0.4 0 0.2 0.9*CVCC CVCC -15 +15 0.1 0.50V -0.25 ...
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... Typical Application Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24B ( AT83C24B if needed) EVCC Host MICROCONTROLLER XTAL1 XTAL2 MHz VSS VSS Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor VCC See note for I/O pull up SDA, Reset ...
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... Typical NDS Application Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. EVCC VCC TWI RST INT0 Px.y Px.y Px.y Px.y Host MICROCONTROLLER XTAL1 XTAL2 18.432 or 27MHz VSS VSS Note: AT83C24 36 See note See note1 for I/O pull up SDA, Reset SCL ...
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... AT83C24B-PRRIL AT83C24B-PRTIM AT83C24B-PRRIM AT83C24B-TISIL AT83C24B-TIRIL AT83C24B-TISIM AT83C24B-TIRIM AT83C24NDS-PRTIL AT83C24NDS-PRRIL AT83C24NDS-PRTIM AT83C24NDS-PRRIM AT83C24NDS-TISIL AT83C24NDS-TIRIL AT83C24NDS-TISIM AT83C24NDS-TIRIM AT83C24B-PRTUL AT83C24B-PRRUL AT83C24B-PRTUM AT83C24B-PRRUM AT83C24B-TISUL AT83C24B-TIRUL AT83C24B-TISUM AT83C24B-TIRUM AT83C24NDS-PRTUL AT83C24NDS-PRRUL AT83C24NDS-PRTUM AT83C24NDS-PRRUM 4234G–SCR–01/07 Supply Voltage Temperature Range ( 5.5V Industrial ( 5.5V Industrial (2) 4.00V to 5.5V Industrial (2) 4 ...
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... Part Number AT83C24NDS-TISUL AT83C24NDS-TIRUL AT83C24NDS-TISUM AT83C24NDS-TIRUM Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement. AT83C24 38 Supply Voltage Temperature Range ( 5.5V Industrial & Green ( 5.5V Industrial & Green (1) 4.00V to 5.5V Industrial & Green (1) 4 ...
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... Package Drawings QFN28 4234G–SCR–01/07 AT83C24 39 ...
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SO28 ...
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... SO28 drawing package (error with SO32). 6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30. Changes from 1. QFN28 new package drawing. 4234D-04/ Clock input parameters for AT83C24 and AT83C24NDS. 4234E - 09/04 Changes from 1. Updated green product ordering information. 4234E - 09/04 to 4234F - 10/05 Changes from 1 ...
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... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’sAtmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © ...