AIC1573 AIC [Analog Intergrations Corporation], AIC1573 Datasheet - Page 16

• Manufacturer Part Number: AIC1573
• Description: 5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller
• Manufacturer: AIC [Analog Intergrations Corporation]

Layout Considerations
Any inductance in the switched current path gener-
ates a large voltage spike during the switching i n -
terval. The voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device
over-voltage stress. Careful component selection
and tight layout of critical components, and short,
wide metal trace minimize the voltage spike.
A ground plane should be used. Locate the input
capacitors (C
Minimize the loop formed by C
MOSFET (Q1) and the lower MOSFET (Q2) as
possible. Connections should be as wide as short
as possible to minimize loop inductance.
The connection between Q1, Q2 and output induc-
tor should be as wide as short as practical. Since
this connection has fast voltage transitions will e a-
sily induce EMI.
The output capacitor (C
close the load as possible. Because minimize the
transient load magnitude for high slew rate requires
low inductance and resistance in circuit board
The AIC1573 is best placed over a quiet ground
plane area. The GND pin should be connected to
the groundside of the output capacitors. Under no
circumstances should GND be returned to a ground
inside the C
pins should be shorted right at the IC. This help to
minimize internal ground disturbances in the IC and
prevents differences in ground potential from dis-
rupting internal circuit operation.
The wiring traces from the control IC to the MOS-
FET gate and source should be sized to carry 1A
current. The traces for OUT2 need only be sized
for 0.5A. Locate COUT2 close to the AIC1573.
The Vcc pin should be decoupled directly to GND
by a 2.2 F ceramic capacitor, trace lengths
should be as short as possible.
IN
, Q1, Q2 loop. The GND and PGND
IN
) close to the power switches.
OUT
) should be located as
IN
, the upper
A multi-layer-printed circuit board is recommended.
Figure 11 shows the connections of the critical
components in the converter. The C
could each represent numerous physical capacitors.
Dedicate one solid layer for a ground plane and
make all critical component ground connections
with vias to this layer.
PWM Output Capacitors
The load transient for the microprocessor core r e-
quires high quality capacitors to supply the high
slew rate (di/dt) current demand.
The ESR (equivalent series resistance) and ESL
(equivalent series inductance) parameters rather
than actual capacitance determine the buck ca-
pacitor values. For a given transient load magnitude,
the output voltage transient change due to the out-
put capacitor can be note by the following equation:
After the initial transient, the ESL dependent term
drops off. Because the strong relationship between
output capacitor ESR and output load transient, the
output capacitor is usually chosen for ESR, not for
capacitance value. A capacitor with suitable ESR
will usually have a larger capacitance value than is
needed for energy storage.
A common way to lower ESR and raise ripple cur-
rent capability is to parallel several capacitors. In
most case, multiple electrolytic capacitors of small
case size are better than a single large case c a-
pacitor.
V
I
OUT
OUT
is transient load current step.
ESR
I
OUT
ESL
I
OUT
T
AIC1573
IN
,
and C
where
16
OUT