PALCE29M16H-25 AMD [Advanced Micro Devices], PALCE29M16H-25 Datasheet - Page 6

• Manufacturer Part Number: PALCE29M16H-25
• Description: 24-Pin EE CMOS Programmable Array Logic
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1 = Erased State (charged or disconnected).
0 = Programmed State (discharged or connected).
*Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch is transparent when the LE pin is LOW.
Active-HIGH LE means the opposite.
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AMD
Table 1b. PALCE29M16 I/O Logic Macrocell Clock Polarity and Output Enable Selections
S
S
1
0
1
0
3
1
Table 1a. PALCE29M16 I/O Logic Macrocell Architecture Selections
I/O Cell
Output Cell
Input Cell
Output Type
Combinatorial
Register/Latch
S
S
1
1
0
0
1
1
0
0
4
6
*Applies to macrocells with single feedback only.
S
S
1
0
1
0
1
0
1
0
5
7
Clock Edge/Latch Enable Level
CLK/LE pin positive-going edge, active-LOW LE
CLK/LE pin negative-going edge, active-HIGH LE
I/CLK/LE pin positive-going edge, active-LOW LE
I/CLK/LE pin negative-going edge, active-HIGH LE
Output Buffer Control
Pin-Controlled Three-State Enable
XOR PT-Controlled Three-State Enable
Permanently Enabled (Output only)
Permanently Disabled (Input only)
S
1
0
PALCE29M16H-25
8
Feedback*
Register/Latch
I/O
S
S
1
0
1
0
2
0
Storage Element
Register
Latch
Output Polarity
Active LOW
Active HIGH