PALCE29M16H-25 AMD [Advanced Micro Devices], PALCE29M16H-25 Datasheet - Page 21

• Manufacturer Part Number: PALCE29M16H-25
• Description: 24-Pin EE CMOS Programmable Array Logic
• Manufacturer: AMD [Advanced Micro Devices]

POWER-UP RESET
The registered devices in the AMD PAL Family have
been designed with the capability to reset during system
power-up. Following power-up, all registers will be reset
to LOW. The output state will depend on the polarity of
the output buffer. This feature provides extra flexibility to
the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the
Parameter
Symbol
t
t
t
PR
t
W
R
S
Active LOW
Registered
Output
Power
Clock
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width
V
CC
Rise Time
t
R
4 V
Power-Up Reset Waveform
PALCE29M16H-25
t
PR
asynchronous operation of the power-up reset, and the
wide range of ways V
conditions are required to ensure a valid power-up re-
set. These conditions are:
The V
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
t
W
CC
t
S
rise must be monotonic.
CC
See Switching Characteristics
can rise to its steady state, two
Min
500
08740G-38
Max
10
V
CC
AMD
Unit
2-347
s
s