PALCE29M16H-25 AMD [Advanced Micro Devices], PALCE29M16H-25 Datasheet - Page 5

• Manufacturer Part Number: PALCE29M16H-25
• Description: 24-Pin EE CMOS Programmable Array Logic
• Manufacturer: AMD [Advanced Micro Devices]

The output polarity for each macrocell in each of the
three modes of operation is user-selectable, allowing
complete flexibility of the macrocell configuration.
Eight of the macrocells (I/OF
pendent feedback paths to the AND array (see Figure
2b). The first is a dedicated I/O pin feedback to the AND
array for combinatorial input. The second path consists
of a direct register/latch feedback to the array. If the pin
is used as a dedicated input using the first feedback
path, the register/latch feedback path is still available to
the AND array. This path provides the capability of using
the register/latch as a buried state register/latch. The
other eight macrocells have a single feedback path to
the AND array. This feedback is user-selectable as
either an I/O pin or a register/latch feedback (see
Figure 2a).
Each macrocell can provide true input/output capability.
The user can select each macrocell register/latch to be
driven by either the signal generated by the AND-OR ar-
ray or the I/O pin. When the I/O pin is selected as the in-
put, the feedback path provides the register/latch input
to the array. When used as an input, each macrocell is
also user-programmable for registered, latched, or com-
binatorial input.
The PALCE29M16H has a dedicated CLK/LE pin and
an I/CLK/LE pin. All macrocells have a programmable
switch to choose between these two pins as the clock or
latch enable signal. These signals are clock signals for
macrocells configured as registers and latch enable sig-
nals for macrocells configured as latches. The polarity of
these CLK/LE signals is also individually programma-
ble. Thus different registers or latches can be driven by
different clocks and clock phases.
The Output-Enable mode of each of the macrocells can
be selected by the user. The I/O pin can be configured
as an output pin (permanently enabled) or as an input
pin (permanently disabled). It can also be configured as
Common Asynchronous Preset
Common Asynchronous Reset
OE PTs For Banks
Common I/OE Pin
of 4 Macrocells
To AND Array
To AND Array
Figure 2b. PALCE29M16 Macrocell (Dual Feedback)
0
I/CLK/LE
–I/OF
CLK/LE
P0
P7
7
) have two inde-
S4
1 1
1 0
0 1
0 0
PALCE29M16H-25
S5
S3
1
0
S2
CLK/LE
a dynamic I/O controlled by the Output Enable pin or by
two AND-XOR product terms which are available for
each bank of four I/O Logic Macrocells.
I/O Logic Macrocell Configuration
AMD’s unique I/O macrocell offers major benefits
through its versatile, programmable input/output cell
structure, multiple clock choices, flexible Output Enable
and feedback selection. Eight I/O macrocells with single
feedback contain 9 EE cells, while the other eight ma-
crocells contain 8 EE cells for programming the input/
output functions (see Table 1).
EE cell S
natorial or registered/latched. S
larity (active-HIGH or active-LOW). S
whether the storage element is a register or a latch. S
allows the use of the macrocell as an input register/latch
or as an output register/latch. It selects the direction of
the data path through the register/latch. If connected to
the usual AND-OR array output, the register/latch is an
output connected to the I/O pin. If connected to the I/O
pin, the register/latch becomes an input register/latch to
the AND array using the feedback data path.
Programmable EE cells S4 and S5 allow the user to se-
lect one of the four CLK/LE signals for each macrocell.
S
trolled, two-product-term-controlled, permanently en-
abled or permanently disabled. S8 controls a feedback
multiplexer for the macrocells with a single feedback
path only.
Using the programmable EE cells S0–S8 various input
and output configurations can be selected. Some of the
possible configuration options are shown in Figure 3.
In the unprogrammed state (charged, disconnected), an
architectural cell is said to have a value of “1”; in the pro-
grammed state (discharged, connected to GND), an ar-
chitectural cell is said to have a value of “0.”
D
Preset
Reset
6
and S
Q
Q
RF X
S0
7
1
are used to control Output Enable as pin con-
V CC
1 1
0 1
1 0
0 0
controls whether the macrocell will be combi-
S1
S6
0 1
1 1
1 0
0 0
S7
0
controls the output po-
I/OF
08740G-5
X
2
determines
AMD
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3