PALCE29M16H-25 AMD [Advanced Micro Devices], PALCE29M16H-25 Datasheet - Page 4

• Manufacturer Part Number: PALCE29M16H-25
• Description: 24-Pin EE CMOS Programmable Array Logic
• Manufacturer: AMD [Advanced Micro Devices]

FUNCTIONAL DESCRIPTION
Inputs
The PALCE29M16 has 29 inputs to drive each product
term (up to 58 inputs with both TRUE and complement
versions available to the AND array) as shown in the
block diagram in Figure 1. Of these 29 inputs, 3 are
dedicated inputs, 16 are from 8 I/O logic macrocells with
two feedbacks, 8 are from other I/O logic macrocells
with single feedback, one is the I/OE input and one is the
I/CLK/LE input.
Initially the AND-array gates are disconnected from all
the inputs. This condition represents a logical TRUE for
the AND array. By selectively programming the EE cells,
the AND array may be connected to either the TRUE in-
put or the complement input. When both the TRUE and
complement inputs are connected, a logical FALSE re-
sults at the output of the AND gate.
Product Terms
The degree of programmability and complexity of a PAL
device is determined by the number of connections that
form the programmable-AND and OR gates. Each pro-
grammable-AND gate is called a product term. The
PALCE29M16 has 188 product terms; 176 of these
product terms provide logic capability and 12 are archi-
tectural or control product terms. Among the 12 control
product terms, two are for common Asynchronous-
Preset and Reset, one is for Observability, and one is for
Preload. The other eight are common Output Enable
product terms. The Output Enable of each bank of four
macrocells can be programmed to be controlled by a
common Output Enable pin or two AND/XOR product
terms. It may be also permanently enabled or perma-
nently disabled.
Each product term on the PALCE29M16 consists of a
58-input AND gate. The outputs of these AND gates are
2-330
AMD
Common Asynchronous Preset
Common Asynchronous Reset
OE PTs For Banks
Common I/OE Pin
of 4 Macrocells
To AND Array
Figure 2a. PALCE29M16 Macrocell (Single Feedback)
P11 or P15
I/CLK/LE
CLK/LE
P0
S4
1 1
1 0
0 1
0 0
PALCE29M16H-25
S8
S5
1
0
S3
1
0
S2
connected to a fixed-OR plane. Product terms are allo-
cated to OR gates in a varied distribution across the de-
vice ranging from 8 to 16 wide, with an average of 11
logic product terms per output. An increased number of
product terms per output allows more complex functions
to be implemented in a single PAL device. This flexibility
aids in implementing functions such as counters, exclu-
sive-OR functions, or complex state machines, where
different states require different numbers of product
terms.
Common asynchronous-Preset and Reset product
terms are connected to all Registered or Latched I/Os.
When the asynchronous-Preset product term is as-
serted (HIGH) all the registers and latches will immedi-
ately be loaded with a HIGH, independent of the clock.
When the asynchronous-Reset product term is asserted
(HIGH) all the registers and latches will be immediately
loaded with a LOW, independent of the clock. The actual
output state will depend on the macrocell polarity selec-
tion. The latches must be in latched mode (not transpar-
ent mode) for the Reset, Preset, Preload, and power-up
Reset modes to be meaningful.
Input/Output Logic Macrocells
The I/O logic macrocell allows the user the flexibility of
defining the architecture of each input or output on an in-
dividual basis. It also provides the capability of using the
associated pin either as an input or an output.
The PALCE29M16 has 16 macrocells, one for each I/O
pin. Each I/O macrocell can be programmed for combi-
natorial, registered or latched operation (see Figure 2).
Combinatorial output is desired when the PAL device is
used to replace combinatorial glue logic. Registers and
Latches are used in synchronous logic applications.
CLK/LE
D
Preset
Reset
Q
Q
S0
R X
V CC
1 1
0 1
1 0
0 0
S1
S6
0 1
1 1
1 0
0 0
S7
I/O
08740G-4
X