PIC18F242 MICROCHIP [Microchip Technology], PIC18F242 Datasheet - Page 73

• Manufacturer Part Number: PIC18F242
• Description: 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

7.0
7.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
TABLE 7-1:
7.2
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
© 2006 Microchip Technology Inc.
MOVF
MULWF
16 x 16 unsigned
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
Routine
8 X 8 HARDWARE MULTIPLIER
Introduction
Operation
ARG1, W
ARG2
PERFORMANCE COMPARISON
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
;
; ARG1 * ARG2 ->
;
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
PRODH:PRODL
Program
Memory
(Words)
13
33
21
24
52
36
1
6
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
EXAMPLE 7-2:
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-1:
RES3:RES0
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
algorithms
Cycles
(Max)
242
254
91
36
69
24
1
6
ARG1,
ARG2
ARG2,
PRODH, F
ARG2,
ARG1,
PRODH, F
=
=
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.4 s
3.6 s
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 2
(ARG1H ARG2L 2
(ARG1L ARG2H 2
(ARG1L ARG2L)
SB
SB
W
W
8 x 8 SIGNED MULTIPLY
ROUTINE
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
PIC18FXX2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
27.6 s
36.4 s
96.8 s
14.4 s
400 ns
Time
9.6 s
2.4 s
DS39564C-page 71
- ARG1
8
8
16
- ARG2
) +
) +
) +
@ 4 MHz
242 s
254 s
69 s
91 s
24 s
36 s
1 s
6 s