PIC18F242 MICROCHIP [Microchip Technology], PIC18F242 Datasheet - Page 136

• Manufacturer Part Number: PIC18F242
• Description: 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18FXX2
15.4
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the Standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) - RC3/SCK/SCL
• Serial data (SDA) - RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 15-7:
DS39564C-page 134
RC3/SCK/SCL
RC4/
SDI/
SDA
I
2
C Mode
Read
Shift
Clock
MSb
MSSP BLOCK DIAGRAM
(I
STOP bit Detect
2
2
Match Detect
SSPADD reg
SSPBUF reg
START and
SSPSR reg
C mode fully implements all
C MODE)
LSb
Write
(SSPSTAT reg)
Internal
Data Bus
S, P bits
Set, Reset
Addr Match
15.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read
only. The upper two bits of the SSPSTAT are read/
write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together,
create a double buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double buff-
ered. A write to SSPBUF will write to both SSPBUF and
SSPSR.
accessible
REGISTERS
© 2006 Microchip Technology Inc.
2
C mode operation. The
2
C Slave mode. When
2
C operation.