KMPC855TZQ50D4 FREESCALE [Freescale Semiconductor, Inc], KMPC855TZQ50D4 Datasheet - Page 69

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KMPC855TZQ50D4

Manufacturer Part Number
KMPC855TZQ50D4
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
13.3
Table 31
Figure 74
13.4
Table 32
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Freescale Semiconductor
Num
Num
M10
M11
M12
M13
M14
M15
M9
MII_CRS, MII_COL minimum pulse width
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII_MDC pulse width high
MII_MDC pulse width low
provides information on the MII async inputs signal timing.
provides information on the MII serial management channel signal timing. The FEC functions
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Table 32. MII Serial Management Channel Timing
Figure 74. MII Async Inputs Timing Diagram
Table 31. MII Async Inputs Signal Timing
Characteristic
Characteristic
M9
Min
1.5
40%
40%
Min
10
0
0
FEC Electrical Characteristics
Max
60%
60%
Max
25
MII_TX_CLK
MII_MDC
MII_MDC
period
period
period
Unit
Unit
ns
ns
ns
ns
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