KMPC855TZQ50D4 FREESCALE [Freescale Semiconductor, Inc], KMPC855TZQ50D4 Datasheet - Page 32

no-image

KMPC855TZQ50D4

Manufacturer Part Number
KMPC855TZQ50D4
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Bus Signal Timing
Figure 20
Figure 21
GPCM.
Figure 22
32
Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
CSx, WE[0:3],
R/W, BURST
TSIZ[0:1],
provides the timing for the synchronous external master access controlled by the GPCM.
provides the timing for the asynchronous external master memory access controlled by the
provides the timing for the asynchronous external master control signals negation.
CLKOUT
OE, GPLx,
TSIZ[0:1],
CLKOUT
Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
A[0:31],
A[0:31],
BS[0:3]
R/W
CSx
Figure 22. Asynchronous External Master—Control Signals Negation Timing
CSx
AS
TS
AS
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
B40
B39
B41
B40
B42
B43
B22
B22
Freescale Semiconductor

Related parts for KMPC855TZQ50D4