KMPC855TZQ50D4 FREESCALE [Freescale Semiconductor, Inc], KMPC855TZQ50D4 Datasheet - Page 59

• Manufacturer Part Number: KMPC855TZQ50D4
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
(Output)
RSTRT
RCLK1
(Input)
TENA(RTS1)
RxD1
Notes:
RENA(CD1)
1.
2.
REJECT
(Output)
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in
the buffer descriptor at the end of the frame transmission.
(Note 2)
TCLK1
(Input)
TxD1
(Input)
0
128
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Figure 62. CAM Interface Receive Start Timing Diagram
133
131
Figure 63. CAM Interface REJECT Timing Diagram
Start Frame Delimiter
Figure 61. Ethernet Transmit Timing Diagram
1
128
1
137
121
BIT1
125
132
129
BIT2
136
CPM Electrical Characteristics
134
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