KMPC855TZQ50D4 FREESCALE [Freescale Semiconductor, Inc], KMPC855TZQ50D4 Datasheet
KMPC855TZQ50D4
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KMPC855TZQ50D4 Summary of contents
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Freescale Semiconductor Technical Data MPC860 PowerQUICC™ Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. To locate published errata or updates for this document, refer to ...
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Overview 1 Overview The MPC860 power quad integrated communications controller (PowerQUICC™ versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The PowerQUICC unit is referred ...
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Features The following list summarizes the key MPC860 features: • Embedded single-issue, 32-bit core (implementing the Power Architecture technology) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch without conditional execution. — 4- ...
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Features • System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) — Reset controller — IEEE 1149.1™ Std. test ...
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Kbytes of dual-port RAM — 16 serial DMA (SDMA) channels — Three parallel I/O registers with open-drain capability • Four baud-rate generators (BRGs) — Independent (can be tied to any SCC or SMC) — Allows changes ...
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Features — Allows dynamic changes — Can be internally connected to six serial channels (four SCCs and two SMCs) • Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on the MPC860 or the ...
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Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC860. provides the maximum ratings. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however advised that ...
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Thermal Characteristics Figure 1 shows the undershoot and overshoot voltages at the interface of the MPC860 DDH DDL V /V DDH DDL V V DDH IH GND – 0 GND – 0.7 V Note: 1. ...
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Table 4 shows the thermal characteristics for the MPC860. Rating Mold Compound Thickness 1 Junction-to-ambient Natural convection Airflow (200 ft/min) 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package top Natural convection 1 Junction temperature is a function of on-chip power dissipation, package ...
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Power Dissipation 5 Power Dissipation Table 5 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice the bus speed. Die Revision D.4 (1:1 mode) D.4 (2:1 mode) ...
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Table 6. DC Electrical Specifications (continued) Characteristic Input leakage current 3.6 V (except TMS, TRST, in DSCK, and DSDI pins) Input leakage current (except TMS, TRST, in DSCK, and DSDI pins) 2 Input capacitance ...
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Thermal Calculation and Measurement 7 Thermal Calculation and Measurement For the following discussions, P drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature θ where ...
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Figure 2. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation θ ...
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Layout Practices where: Ψ = thermal characterization parameter thermocouple temperature on top of package power dissipation in package D The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type ...
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Bus Signal Timing Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz. The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed bus ...
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Bus Signal Timing Num Characteristic B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z B11 CLKOUT to TS, BB assertion B11a CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA ...
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Num Characteristic B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0, and CSNT = 0 B24 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 0 B24a ...
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Bus Signal Timing Num Characteristic B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 B29e CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ...
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Num Characteristic B31a CLKOUT falling edge to CS valid—as requested by control bit CST1 in the corresponding word in UPM B31b CLKOUT rising edge to CS valid—as requested by control bit CST2 in the corresponding word in UPM B31c CLKOUT ...
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Bus Signal Timing Num Characteristic B35 A(0:31), BADDR(28:30 valid—as requested by control bit BST4 in the corresponding word in UPM B35a A(0:31), BADDR(28:30), and D(0:31 valid—as requested by control bit BST1 in the corresponding word in ...
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Figure 3 is the control timing diagram. CLKOUT B Outputs Outputs Inputs Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 4 provides the timing ...
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Bus Signal Timing Figure 5 provides the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 5. Synchronous Output Signals Timing Figure 6 provides the timing for the synchronous active pull-up and ...
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Figure 7 provides the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 7. Synchronous Input Signals Timing Figure 8 provides normal case timing for input data. It also applies to normal ...
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Bus Signal Timing Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling ...
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CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) ...
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Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B12 B8 B22a ...
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Figure 14 through Figure 16 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT TS A[j0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = ...
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Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B11 B12 B8 B28b B28d B22 ...
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CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B12 B8 B22 B25 B26 B8 Bus ...
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Bus Signal Timing Figure 17 provides the timing for the external bus controlled by the UPM. CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 17. External Bus Timing (UPM Controlled Signals) MPC860 PowerQUICC™ Family Hardware Specifications, Rev ...
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Figure 18 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 19 provides the timing for ...
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Bus Signal Timing Figure 20 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 21 provides ...
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Table 8 provides interrupt timing for the MPC860. Num I39 IRQx valid to CLKOUT rising edge (setup time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high I43 IRQx edge-to-edge time 1 The ...
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Bus Signal Timing Table 9 shows the PCMCIA timing for the MPC860. Num Characteristic P44 A(0:31), REG valid to PCMCIA Strobe 1 asserted P45 A(0:31), REG valid to ALE negation P46 CLKOUT to REG valid P47 CLKOUT to REG invalid ...
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Figure 25 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 25. PCMCIA Access Cycle Timing External Bus Read MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor ...
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Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS A[0:31] REG CE1/CE2 PCWE, IOWR ALE D[0:31] Figure 26. PCMCIA Access Cycle Timing External Bus Write Figure 27 provides the PCMCIA WAIT ...
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Table 10 shows the PCMCIA port timing for the MPC860. Num Characteristic P57 CLKOUT to OPx valid P58 HRESET negated to OPx drive P59 IP_Xx valid to CLKOUT rising edge P60 CLKOUT rising edge to IP_Xx invalid 1 OP2 and ...
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Bus Signal Timing Table 11 shows the debug port timing for the MPC860. Num Characteristic P61 DSCK cycle time P62 DSCK clock pulse width P63 DSCK rise and fall times P64 DSDI input data setup time P65 DSDI data hold ...
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Table 12 shows the reset timing for the MPC860. Num Characteristic R69 CLKOUT to HRESET high impedance R70 CLKOUT to SRESET high impedance R71 RSTCONF pulse width R72 — R73 Configuration data to HRESET rising edge setup time R74 Configuration ...
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Bus Signal Timing Figure 32 shows the reset timing for the data bus configuration. HRESET RSTCONF D[0:31] (IN) Figure 32. Reset Timing—Configuration from Data Bus Figure 33 provides the reset timing for the data bus weak drive during configuration. CLKOUT ...
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Figure 34 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 34. Reset Timing—Debug Port Configuration 10 IEEE 1149.1 Electrical Specifications Table 13 provides the JTAG timings for the MPC860 shown in Num J82 TCK ...
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IEEE 1149.1 Electrical Specifications TCK TCK TMS, TDI TDO Figure 36. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 38. Boundary Scan (JTAG) Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 ...
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CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC860. 11.1 PIP/PIO AC Electrical Specifications Table 14 provides the PIP/PIO AC timings as shown in Num 21 Data-in ...
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CPM Electrical Characteristics DATA-OUT STBO (Output) STBI (Input) Figure 40. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 41. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 42. PIP TX (Pulse Mode) ...
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CLKO DATA-IN DATA-OUT Figure 43. Parallel I/O Data-In/Data-Out Timing Diagram 11.2 Port C Interrupt AC Electrical Specifications Table 15 provides the timings for port C interrupts. Num 35 Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt ...
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CPM Electrical Characteristics Table 16. IDMA Controller Timing (continued) Num 42 SDACK assertion delay from clock high 43 SDACK negation delay from clock low 44 SDACK negation delay from TA low 45 SDACK negation delay from clock high 46 TA ...
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CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 47. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 48. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC860 PowerQUICC™ Family Hardware ...
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CPM Electrical Characteristics 11.4 Baud Rate Generator AC Electrical Specifications Table 17 provides the baud rate generator timings as shown in Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle 50 BRGOX Figure 49. Baud ...
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CLKO 61 TIN/TGATE (Input) TOUT (Output) Figure 50. CPM General-Purpose Timers Timing Diagram 11.6 Serial Interface AC Electrical Specifications Table 19 provides the serial interface timings as shown in Num 70 L1RCLK, L1TCLK frequency (DSC = 0) 71 L1RCLK, L1TCLK ...
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CPM Electrical Characteristics Num 84 L1CLK edge to L1CLKO valid (DSC = 1) 85 L1RQ valid before falling edge of L1TSYNC 2 86 L1GR setup time 87 L1GR hold time 88 L1CLK edge to L1SYNC valid (FSD = 00) CNT ...
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L1RCLK ( (Input) 82 L1RCLK ( (Input) L1RSYNC (Input) 73 L1RXD (Input) 76 L1ST(4–1) (Output) L1CLKO (Output) Figure 52. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC860 PowerQUICC™ ...
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CPM Electrical Characteristics L1TCLK ( (Input) 71 L1TCLK ( (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4–1) (Output) Figure 53. SI Transmit Timing Diagram (DSC = 0) MPC860 PowerQUICC™ Family Hardware ...
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L1RCLK ( (Input) L1RCLK ( (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 L1ST(4–1) (Output) 84 L1CLKO (Output) Figure 54. SI Transmit Timing with Double Speed Clocking (DSC = 1) ...
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CPM Electrical Characteristics MPC860 PowerQUICC™ Family Hardware Specifications, Rev Figure 55. IDL Timing Freescale Semiconductor ...
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SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Num 100 RCLK1 and TCLK1 width high 101 RCLK1 and TCLK1 width low 102 RCLK1 and TCLK1 rise/fall time 103 TXD1 active delay (from TCLK1 ...
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CPM Electrical Characteristics Figure 56 through Figure 58 show the NMSI timings. RCLK1 102 106 RxD1 (Input) CD1 (Input) CD1 (SYNC Input) Figure 56. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) ...
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TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Echo Input) 11.8 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Num 120 CLSN width high 121 RCLK1 rise/fall time 122 RCLK1 width low 1 123 RCLK1 clock period ...
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CPM Electrical Characteristics Num 135 RSTRT active delay (from TCLK1 falling edge) 136 RSTRT inactive delay (from TCLK1 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK negated 1 The ratios SYNCCLK/RCLK1 ...
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TCLK1 128 131 TxD1 (Output) 133 TENA(RTS1) (Input) RENA(CD1) (Input) (Note 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then ...
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CPM Electrical Characteristics 11.9 SMC Transparent AC Electrical Specifications Table 23 provides the SMC transparent timings as shown in Num 1 150 SMCLK clock period 151 SMCLK width low 151A SMCLK width high 152 SMCLK rise/fall time 153 SMTXD active ...
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SPI Master AC Electrical Specifications Table 24 provides the SPI master timings as shown in Num 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master data hold time ...
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CPM Electrical Characteristics SPICLK ( (Output) 161 161 SPICLK ( (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI (Output) Figure 66. SPI Master ( Timing Diagram 11.11 SPI Slave AC Electrical Specifications Table 25 ...
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SPISEL (Input) SPICLK ( (Input) 173 173 SPICLK ( (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 67. SPI Slave ( Timing Diagram SPISEL (Input) 171 SPICLK ( (Input) ...
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CPM Electrical Characteristics 2 11. Electrical Specifications 2 Table 26 provides the I C (SCL < 100 kHz) timings. Num 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions 203 ...
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Figure 69 shows the I C bus timing. SDA 202 205 SCL 206 12 UTOPIA AC Electrical Specifications Table 28 shows the AC electrical specifications for the UTOPIA interface. Table 28. UTOPIA AC Electrical Specifications Num Signal Characteristic U1 ...
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UTOPIA AC Electrical Specifications Figure 70 shows signal timings during UTOPIA receive operations. UtpClk U5 PHREQ n RxClav RxEnb UTPB SOC Figure 71 shows signal timings during UTOPIA transmit operations. UtpClk U5 5 PHSEL n TxClav TxEnb UTPB SOC MPC860 ...
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FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL ...
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FEC Electrical Characteristics 13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed ...
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MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 31 provides information on the MII async inputs signal timing. Num M9 MII_CRS, MII_COL minimum pulse width Figure 74 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL Figure 74. ...
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Mechanical Data and Ordering Information Figure 75 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 75. MII Serial Management Channel Timing Diagram 14 Mechanical Data and Ordering Information Table 33 provides information on ...
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... ZP/ZQ MPC855TZQ50D4 0° to 95°C MPC860DEZQ50D4 MPC860DTZQ50D4 MPC860ENZQ50D4 MPC860SRZQ50D4 MPC860TZQ50D4 MPC860DPZQ50D4 MPC860PZQ50D4 Tape and Reel MPC855TZQ50D4R2 MPC860DEZQ50D4R2 MPC860ENZQ50D4R2 MPC860SRZQ50D4R2 MPC860TZQ50D4R2 MPC860DPZQ50D4R2 Sample KMPC855TZQ50D4 KMPC860DEZQ50D4 KMPC860DTZQ50D4 KMPC860TZQ50D4 KMPC860SRZQ50D4 1 66 ZP/ZQ MPC855TZQ66D4 0° to 95°C MPC860DEZQ66D4 MPC860DTZQ66D4 MPC860ENZQ66D4 MPC860SRZQ66D4 MPC860TZQ66D4 MPC860DPZQ66D4 MPC860PZQ66D4 Tape and Reel MPC860SRZQ66D4R2 ...
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Mechanical Data and Ordering Information Table 34. MPC860 Family Package/Frequency Availability (continued) Package Type Ball grid array (CZP suffix) CZP suffix—leaded CZQ suffix—leaded CVR suffix—lead-free are available as needed 1 The ZP package is no longer recommended for use. The ...
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Pin Assignments Figure 76 shows the top view pinout of the PBGA package. For additional information, see the MPC860 PowerQUICC User’s Manual, or the MPC855T User’s Manual. PD10 PD8 PD3 IRQ7 PD14 PD13 PD9 PD6 M_Tx_EN PA0 PB14 PD15 ...
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Mechanical Data and Ordering Information 14.2 Mechanical Dimensions of the PBGA Package Figure 77 shows the mechanical dimensions of the ZP PBGA package TOP VIEW ...
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Figure 78 shows the mechanical dimensions of the ZQ PBGA package. 1. All Dimensions in millimeters. 2. Dimensions and tolerance per ASME Y14.5M, 1994. 3. Maximum Solder Ball Diameter measured parallel to Datum A. 4. Datum A, the seating plane, ...
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Document Revision History 15 Document Revision History Table 35 lists significant changes between revisions of this hardware specification. Revision Date 5.1 11/2001 • Revised template format, removed references to MAC functionality, changed B23 max value @ 66 MHz from 2ns ...
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THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Document Revision History 77 ...
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Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev Freescale Semiconductor ...
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THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Document Revision History 79 ...
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