PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 136

• Manufacturer Part Number: PIC17C752
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

15.2.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 15-15: I
FIGURE 15-16: I
DS30264A-page 136
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
SDA
SCL
SSPIF (PIR2<7>)
Note:
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S
S
SLAVE RECEPTION
The SSPBUF will be loaded if the SSPOV
bit = 1 and the BF flag = 0. If a read of the
SSPBUF was performed, but the user did
not clear the state of the SSPOV bit before
the next receive occured. The ACK is not
sent and the SSPBUF is updated.
A7 A6 A5 A4 A3 A2 A1
1
A7
2
1
Data in
sampled
Receiving Address
2
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
4
A5
Receiving Address
3
5
A4
4
6
7
A3
5
R/W=0
8
A2
6
ACK
9
A1
7
D7
1
D6
R/W = 1
2
8
SSPBUF register is read
Cleared in software
Preliminary
Receiving Data
D5
3
9
ACK
responds to SSPIF
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
while CPU
SCL held low
D3
5
D2
6
15.2.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCLpin is held low. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then SCL pin
should be enabled by setting bit CKP (SSPCON1<4>).
The master must monitor the SCL pin prior to asserting
another clock pulse. The slave devices may be holding
off the master by stretching the clock. The eight data
bits are shifted out on the falling edge of the SCL input.
This ensures that the SDA signal is valid during the
SCL high time (Figure 15-16).
D1
7
D7
1
SSPBUF is written in software
D0
8
ACK
D6
9
cleared in software
2
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D7
SLAVE TRANSMISSION
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
1997 Microchip Technology Inc.
5
D2
6
D2
6
From SSP interrupt
service routine
D1
7
D1
7
D0
8
D0
8
ACK
ACK
9
9
transfer
Bus Master
terminates
P
P