PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 124

• Manufacturer Part Number: PIC17C752
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 15-4: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
DS30264A-page 124
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0 R/W-0
SMP
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 15-8, Figure 15-11, and Figure 15-12)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress. Or’ing this bit with SAE, RCE, SPE, or AKE will indicate if the SSP is in
IDLE mode.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Data Transmit in progress (does not include ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include ACK and stop bits), SSPBUF is empty
CKE
2
2
2
C master or slave mode:
C slave mode:
C master mode:
R-0
D/A
2
C mode only)
2
2
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
2
R-0
C modes)
P
2
C slave mode only)
2
C slave mode only)
R-0
S
2
C mode only)
Preliminary
R/W
R-0
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’