PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 84
![no-image](/images/no-image-200.jpg)
PIC12F1516
Manufacturer Part Number
PIC12F1516
Description
28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC12F1516.pdf
(344 pages)
- Current page: 84 of 344
- Download datasheet (4Mb)
PIC16(L)F1516/7/8/9
7.6.5
The PIR2 register contains the interrupt flag bits, as
shown in
REGISTER 7-5:
DS41452B-page 84
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6-4
bit 3
bit 2-1
bit 0
R/W-0/0
OSFIF
Register
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
7-5.
U-0
—
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCLIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
—
software
2011 Microchip Technology Inc.
should
U-0
—
ensure
R/W-0/0
CCP2IF
bit 0
the
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