PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 206

• Manufacturer Part Number: PIC12F1516
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC16(L)F1516/7/8/9
21.5.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see
“Clock Stretching”
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
21.5.3.1
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPCON3 register is set, the
BCLIF bit of the PIR register is set. Once a bus collision
is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
DS41452B-page 206
SLAVE TRANSMISSION
Slave Mode Bus Collision
for more detail). By stretching the
Section 21.5.6
Preliminary
21.5.3.2
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do
Figure 21-17
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. SSPIF is set after the ACK response from the
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
13. Steps 9-13 are repeated for each transmitted
14. If the master sends a not ACK; the clock is not
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Note 1: If the master ACKs the clock will be
Master sends a Start condition on SDA and
SCL.
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit set is received by
the Slave setting SSPIF bit.
Slave hardware generates an ACK and sets
SSPIF.
SSPIF bit is cleared by user.
Software reads the received address from
SSPBUF, clearing BF.
R/W is set so CKP was automatically cleared
after the ACK.
The slave software loads the transmit data into
SSPBUF.
CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
master is loaded into the ACKSTAT register.
see if the master wants to clock out more data.
byte.
held, but SSPIF is still set.
to
2: ACKSTAT is the only bit updated on the
accomplish
stretched.
rising edge of SCL (9th) rather than the
falling.
can be used as a reference to this list.
7-bit Transmission
 2011 Microchip Technology Inc.
a
standard
transmission.