PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 131

• Manufacturer Part Number: PIC12F1516
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
TABLE 12-11: SUMMARY OF CONFIGURATION WORD WITH PORTE
 2010 Microchip Technology Inc.
CONFIG1
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3
bit 2-0
Note 1:
ADCON0
ANSELE
CCPxCON
LATE
PORTE
TRISE
WPUE
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Note 1: These bits are not implemented on the PIC16(L)F1516/8 devices, read as ‘0’.
Name
Name
U-0
—
2:
(1)
— = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by PORTE.
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
PORTE.
13:8
Bits
7:0
Unimplemented: Read as ‘0’
WPUE: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
Bit 7
—
—
—
—
—
—
—
Bit -/7
U-0
CP
—
Bit 6
—
—
—
—
—
—
MCLRE
Bit -/6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
Bit 5
PWRTE
Bit 13/5
FCMEN
—
—
—
—
—
DCxB<1:0>
CHS<4:0>
U-0
Preliminary
—
Bit 4
—
—
—
—
—
Bit 12/4
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
WPUE3
R/W-1/1
WPUE3
Bit 3
RE3
CLKOUTEN
—
—
‘1’
Bit 11/3
PIC16(L)F1516/7/8/9
TRISE2
LATE2
ANSE2
RE2
Bit 2
—
CCPxM<3:0>
Bit 10/2
(1)
U-0
(1)
(1)
—
BOREN<1:0>
GO/DONE
TRISE1
LATE1
ANSE1
RE1
FOSC<2:0>
Bit 1
—
Bit 9/1
(1)
(1)
(1)
U-0
—
TRISE0
LATE0
ANSE0
ADON
RE0
Bit 0
DS41452B-page 131
—
Bit 8/0
—
(1)
(1)
(1)
Register
on Page
U-0
Register
on Page
—
147
130
184
130
129
129
131
46
bit 0