MPC82E52AE MEGAWIN [Megawin Technology Co., Ltd], MPC82E52AE Datasheet - Page 18

• Manufacturer Part Number: MPC82E52AE
• Description: 8-bit micro-controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

18
NVM register: OR3 (Option Register 3):
reserved1:= The bit is reserved for afterward user, and should be left at set.
OSCDN: = Used to adjust the behavior of crystal oscillator.
ENROSC: = Used to determined if to enable the built-in RC oscillator.
HWENW: = Hardware Enable Watch-dog-timer
HWWIDL: = Hardware enables reset from Watch-dog-timer in spite of the MCU lies idle.
{HWPS2, HWPS1, HWPS0}: = Hardware Watch-dog-timer Pre-Scalar
reserved1
The user must not clear the bi; otherwise, there could be inadvertent effect impacted on the
device.
Bit-7
If the bit HWENW is cleared to 0, those bits will be loaded into SFR WDTCR after power-up.
Those three bits set the pre-scalar of the watch-dog-timer.
If the bit HWENW is left 1, those three bits makes no sense.
0: =
1: = (default)
0: =
1: = (default)
0: =
1: = (default)
0: =
Watch-dog-timer is also suspended while the MCU lies idle.
1: = (default)
{0,0,0}: =
{0,0,1}: =
{0,1,0}: =
{0,1,1}: =
{1,0,0}: =
{1,0,1}: =
Enable watch-dog-timer to keep working in spite of the MCU has been put into idle mode.
If the bit HWENW is left 1, the bits HWWIDL, HWPS2, HWPS1 and HWPS0 make no sense.
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
The current gain of crystal oscillator amplifier is reduced. It will bring
help to EMI reducing and improve the power consumption. Dealing with application does
not need high frequency clock (under 12 MHz). It is recommended to do so.
The current gain of crystal oscillator is enough for oscillator to start oscillating up to 24 MHz.
Clearing the bit will enable the built-in RC oscillator, and set that oscillator as the oscillating
source
Setting the bit means to disable the built-in RC oscillator.
Clearing the bit will automatically enable the watch-dog-timer after power-up immediately.
HWWIDL, HWPS2, HWPS1 and HWPS0 will be loaded Into SFR WDTCR after power-up if
and only if HWENW =0.
No Hardware Enable for Watch-dog-timer.
The frequency of the clock source for the watch-dog-timer is divided by 2.
The frequency of the clock source for the watch-dog-timer is divided by 4.
The frequency of the clock source for the watch-dog-timer is divided by 8.
The frequency of the clock source for the watch-dog-timer is divided by 16
The frequency of the clock source for the watch-dog-timer is divided by 32
reserved1
Bit-6
HWENW
Bit-5
MPC82x52A Data Sheet
Bit-4
-
HWWIDL
Bit-3
HWPS2
Bit-2
HWPS1
Bit-1
MEGAWIN
HWPS0
Bit-0